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參數(shù)資料
| 型號： | DS21FT42 |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 86/145頁 |
| 文件大小： | 466K |
| 代理商： | DS21FT42 |
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DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1236
TDB2
TDB1
TDC2.1
TDC2.0
DS0 Bit 2 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 1 Suppress Enable.
LSB of the DS0. Set to one to stop this bit
from being used.
19.2
LEGACY FDL SUPPORT
19.2.1
Overview
The DS21Q42 maintains the circuitry that existed in the previous generation of Dallas
Semiconductor’s single chip transceivers and quad framers. Section 19.2 covers the circuitry
and operation of this legacy functionality. In new applications, it is recommended that the
HDLC controller and BOC controller described in Section 19.1 be used. On the receive
side, it is possible to have both the new HDLC/BOC controller and the legacy hardware
working at the same time. However this is not possible on the transmit side since their can
be only one source the of the FDL data internal to the device.
19.2.2
Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the
Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms
(8 times 250 us). The framer will signal an external microcontroller that the buffer has filled
via the SR2.4 bit. If enabled via IMR2.4, the INT* pin will toggle low indicating that the
buffer has filled and needs to be read. The user has 2 ms to read this data before it is lost. If
the byte in the RFDL matches either of the bytes programmed into the RMTCH1 or
RMTCH2 registers, then the SR2.2 bit will be set to a one and the INT* pin will toggled
low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the
FDL or Fs pattern until an important event occurs.
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both
ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD
protocol. The LAPD protocol states that no more than 5 ones should be transmitted in a
row so that the data does not resemble an opening or closing flag (01111110) or an abort
signal (11111111). If enabled via CCR2.0, the DS21Q42 will automatically look for 5 ones
in a row, followed by a zero. If it finds such a pattern, it will automatically remove the zero.
If the zero destuffer sees six or more ones in a row followed by a zero, the zero is not
removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting
the FDL. More on how to use the DS21Q42 in FDL applications in this legacy support
mode is covered in a separate Application Note.
RFDL: RECEIVE FDL REGISTER
(Address = 28 Hex)
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