參數(shù)資料
型號(hào)： DS21FT42
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 17/145頁
文件大?。?/td> 466K
代理商： DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1237
Frames to D4, ESF, and SLC–96 R formats
Each of the four framers contain dual two–frame elastic store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Extracts and inserts robbed bit signaling
Detects and generates yellow (RAI) and blue (AIS) alarms
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality
Generates and detects in–band loop codes from 1 to 8 bits in length including CSU loop
codes
Contains ANSI one’s density monitor and enforcer
Large path and line error counters including BPV, CV, CRC6, and framing bit errors
Pin compatible with DS21Q44 E1 Enhanced Quad E1 Framer
3.3V supply with 5V tolerant I/O; low power CMOS
Available in 128–pin TQFP package
Functional Description
The receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, blue (AIS) and
yellow alarms. If needed, the receive side elastic store can be enabled in order to absorb the
phase and frequency differences between the recovered T1 data stream and an asynchronous
backplane clock which is provided at the RSYSCLK input. The clock applied at the
RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK
can be a burst clock with speeds up to 8.192 MHz.
The transmit side of the DS21Q42 is totally independent from the receive side in both the
clock requirements and characteristics. Data off of a backplane can be passed through a
transmit side elastic store if necessary. The transmit formatter will provide the necessary
frame/multiframe data overhead for T1 transmission.
Reader’s Note:
This data sheet assumes a particular nomenclature of the T1 operating
environment. In each 125 us frame, there are 24 eight–bit channels plus a framing bit. It is
assumed that the framing bit is sent first followed by channel 1. Each channel is made up of
eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit
number 8 is the LSB and is transmitted last. Throughout this data sheet, the following
abbreviations will be used:
D4
SLC–96
Superframe (12 frames per multiframe) Multiframe Structure
Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT42N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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