參數(shù)資料
型號: DS21FT42
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 88/145頁
文件大?。?/td> 466K
代理商: DS21FT42
DALLAS SEMICONDUCTOR
DS21FF42/DS21FT42
101899
/1238
such a pattern, it will automatically insert a zero after the five ones. The CCR2.0 bit should
always be set to a one when the framer is inserting the FDL. More on how to use the
DS21Q42 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER
(Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 19.3]
(MSB)
TFDL7
(LSB)
TFDL0
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
SYMBOL
TFDL7
TFDL0
POSITION
TFDL.7
TFDL.0
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a
byte basis into the outgoing T1 data stream. The LSB is transmitted first.
19.3
D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern.
To allow the device to properly insert the Fs framing pattern, the TFDL register at address
7Eh must be programmed to 1Ch and the following bits must be programmed as shown:
TCR1.2=0 (source Fs data from the TFDL register) CCR2.5=1 (allow the TFDL register to
load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the these
message fields via the TFDL and RFDL registers. Please see the separate Application Note
for a detailed description of how to implement a SLC–96
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