參數(shù)資料
型號: AK5700VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述: 16位ツヒ單聲道ADC,帶鎖相環(huán)
文件頁數(shù): 58/61頁
文件大?。?/td> 519K
代理商: AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 58 -
3. PLL Slave Mode (MCKI pin)
External MCKI
PMPLL bit
(Addr:11H, D0)
Input
(1)
(3)
MCKO bit
(Addr:16H, D2)
(2)
Example
Audio I/F Format: I2S
PLL Reference clock: MCKI
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1) Addr:11H, Data:10H
(3) Stop the external clocks
(2) Addr:16H, Data:00H
Figure 51. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1”
“0”
(2) Stop MCKO output: MCKO bit = “1”
“0”
(3) Stop the external master clock.
4. EXT Slave Mode
EXLRCK
Input
(1)
EXBCLK
Input
(1)
External MCKI
Input
(1)
Example
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop the external clocks
Figure 52. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, EXBCLK and EXLRCK clocks.
* Clock stop sequence is the same for Bypass Mode.
5. EXT Master Mode
LRCK
Output
BCLK
Output
External MCKI
Input
(1)
"H" or "L"
"H" or "L"
Example
Audio I/F Format :I2S
Input MCKI frequency:256fs
Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 53. Clock Stopping Sequence (5)
<Example>
(1) Stop MCKI. BCLK and LRCK are fixed to “H” or “L”.
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