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參數(shù)資料
| 型號： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 49/61頁 |
| 文件大小： | 519K |
| 代理商： | AK5700VN |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 49 -
CONTROL SEQUENCE
Clock Set up
When ADC is powered-up, the clocks must be supplied.
1. PLL Master Mode.
BCLK pin
LRCK pin
MCKO bit
(Addr:16H, D2)
PMPLL bit
(Addr:11H, D0)
40msec(max)
Output
(1)
(6)
Power Supply
PDN pin
PMVCM bit
(Addr:10H, D2)
(2)
(3)
MCKI pin
(5)
(4)
Input
M/S bit
(Addr:11H, D1)
MCKO pin
Output
(8)
(7)
40msec(max)
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L”
“H”
(3)Addr:10H, Data:04H
(2)Addr:11H, Data:12H
Addr:14H, Data:23H
Addr:15H, Data:2FH
(4)Addr:16H, Data:04H
Addr:11H, Data:13H
MCKO, BCLK and LRCK output
Figure 41. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin “L”
“H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows.
(2a) M/S bit = “1” and setting of PLL3-0, FS3-0, BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(3) Power UpVCOM: PMVCM bit = “0”
“1”
VCOM should first be powered-up before the other block operates.
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source.
PLL lock time is 40ms(max) at MCKI=12MHz (Table 4).
(6) The AK5700 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation
starts.
(7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”.
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