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參數(shù)資料
| 型號： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 41/61頁 |
| 文件大小： | 519K |
| 代理商： | AK5700VN |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 41 -
Register Definitions
Addr
Register Name
10H
Power Management
Default
PMADC: MIC-Amp and ADC Power Management
0: Power down (Default)
1: Power up
When the PMADC bit is changed from “0” to “1”, the initialization cycle (3088/fs=70.0ms@fs= 44.1kHz,
HPF1-0 bits = “00”) starts. After initializing, digital data of the ADC is output.
PMVCM: VCOM Power Management
0: Power down (Default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when PMADC=PMPLL=PMMP=MCKO bits = “0”.
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When PMVCM, PMADC, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values remain
unchanged. Power supply current is 20
μ
A(typ) in this case. For fully shut down (typ. 1
μ
A), PDN pin should be “L”.
When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be
present.
Addr
Register Name
D7
D6
D5
11H
PLL Control
0
0
PLL3
Default
0
0
1
PMPLL: PLL Power Management
0: EXT Mode and Power Down (Default)
1: PLL Mode and Power up
M/S: Master / Slave Mode Select
0: Slave Mode (Default)
1: Master Mode
PLL3-0: PLL Reference Clock Select (See Table 4)
Default: “1001”(MCKI pin=12MHz)
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
D1
0
0
D0
PMVCM
0
PMADC
0
D4
PLL2
0
D3
PLL1
0
D2
PLL0
1
D1
M/S
0
D0
PMPLL
0
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