參數(shù)資料
型號(hào)： AK5700VN
廠(chǎng)商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述： 16位ツヒ單聲道ADC，帶鎖相環(huán)
文件頁(yè)數(shù)： 27/61頁(yè)
文件大?。?/td> 519K
代理商： AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 27 -
EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is
selected by FS1-0 bits (see Table 12).
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Frequency
256fs
1024fs
512fs
256fs
Sampling Frequency
Range
7.35kHz
～
48kHz
7.35kHz
～
13kHz
7.35kHz
～
26kHz
7.35kHz
～
48kHz
0
1
2
3
Don’t care
Don’t care
Don’t care
Don’t care
0
0
1
1
0
1
0
1
Default
Table 12. MCKI Frequency at EXT Master Mode
MCKI should always be present whenever the ADC is in operation (PMADC bit = “1”). If MCKI is not provided, the
AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the ADC should be in the power-down mode (PMADC bits = “0”).
AK5700
DSP or
μ
P
MCKI
BCLK
LRCK
SDTO
BCLK
LRCK
SDTI
MCKO
1fs
32fs or 64fs
MCLK
256fs, 512fs or 1024fs
Figure 23. EXT Master Mode
BCKO1 bit
BCKO0 bit
BCLK Output
Frequency
N/A
32fs
64fs
N/A
0
0
1
1
Table 13. BCLK Output Frequency at Master Mode
0
1
0
1
Default
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