參數(shù)資料
型號(hào): AK5700VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述: 16位ツヒ單聲道ADC,帶鎖相環(huán)
文件頁(yè)數(shù): 50/61頁(yè)
文件大?。?/td> 519K
代理商: AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 50 -
2. PLL Slave Mode (EXLRCK or EXBCLK pin)
PMPLL bit
(Addr:11H, D0)
Internal Clock
(1)
Power Supply
PDN pin
PMVCM bit
(Addr:10H, D2)
(2)
(3)
EXLRCK pin
EXBCLK pin
(4)
(5)
Input
4fs of
“H”
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(3) Addr:10H, Data:04H
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
(4) Addr:11H, Data:0DH
Figure 42. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L”
“H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
“1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin) is
supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4).
(5) Normal operation stats after that the PLL is locked.
相關(guān)PDF資料
PDF描述
AK5701KN 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
AK5701_07 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
AK5701VN 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
AK5701 digital audio 16bit A/D converter
AK5702 4-Channel ADC with PLL & MIC-AMP
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