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參數(shù)資料
| 型號(hào)： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 23/61頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AK5700VN |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 23 -
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(See Table 6).
FS3 bit
FS2 bit
FS1 bit
Mode
FS0 bit
Sampling Frequency
Range
7.35kHz
≤
fs
≤
12kHz
12kHz < fs
≤
24kHz
24kHz < fs
≤
48kHz
N/A
0
1
2
0
0
1
0
1
Don’t care
Don’t care
Don’t care
Others
Don’t care
Don’t care
Don’t care
Default
Don’t care
Others
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 7).
In DSP Mode 0, BCLK and LRCK start to output corresponding to Ach data after PLL goes to lock state by setting
PMPLL bit = “0”
“1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0, BCLK “H” time of the first pulse
becomes shorter by 1/(256fs) than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
After that PMPLL bit “0”
“1”
“L” Output
PLL Unlock (except above case)
“L” Output
PLL Lock
“L” Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC outputs invalid data when
the PLL is unlocked.
MCKO bit = “1”
Invalid
Invalid
See Table 9
BCLK pin
LRCK pin
“L” Output
Invalid
See Table 10
“L” Output
Invalid
1fs Output
MCKO pin
PLL State
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
Invalid
Invalid
See Table 9
After that PMPLL bit “0”
“1”
PLL Unlock (except above case)
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
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