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參數(shù)資料
| 型號： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 39/61頁 |
| 文件大小： | 519K |
| 代理商： | AK5700VN |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 39 -
Serial Control Interface
Internal registers may be written by using the 3-wire μP interface pins (CSN, CCLK and CDTI). CSP pin selects the
polarity of CSN pin and chip address.
1) CSP pin = “L”
The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“
↑
”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“
↑
”) after CSN falling edge(“
↓
”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
CCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15
CDTI
C1 C0
A2
A3
A1 A0
A4
D7 D6 D5 D4 D3 D2 D1 D0
R/W
C1-C0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
R/W:
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
A4-A0: Register Address
D7-D0: Control data
“1”
“0”
“1”
Figure 37. Serial Control I/F Timing (CSP pin = “L”)
2) CSP pin = “H”
The data on this interface consists of a 2-bit Chip address (Fixed to “01”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“
↑
”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“
↑
”) after CSN rising edge(“
↑
”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
CCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15
CDTI
C1 C0
A2
A3
A1 A0
A4
D7 D6 D5 D4 D3 D2 D1 D0
R/W
C1-C0: Chip Address (C1 = “0”, C0 = “1”); Fixed to “01”
R/W:
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
A4-A0: Register Address
D7-D0: Control data
“1”
“1”
“0”
Figure 38. Serial Control I/F Timing (CSP pin = “H”)
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