參數(shù)資料
型號(hào)： AK5700VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述： 16位ツヒ單聲道ADC，帶鎖相環(huán)
文件頁(yè)數(shù)： 25/61頁(yè)
文件大?。?/td> 519K
代理商： AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 25 -
PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to MCKI, EXBCLK or EXLRCK pin. The required clock to
the AK5700 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4).
a) PLL reference clock: MCKI pin
EXBCLK and EXLRCK inputs should be synchronized with MCKO output. The phase between MCKO and EXLRCK
dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by
MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5).
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5700
DSP or
μ
P
MCKO
EXBCLK
EXLRCK
SDTO
BCLK
LRCK
SDTI
MCKI
1fs
≥
32fs
MCLK
256fs/128fs/64fs/32fs
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation
(PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
should be in the power-down mode (PMADC bit = “0”).
b) PLL reference clock: EXBCLK or EXLRCK pin
Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).
AK5700
DSP or
μ
P
MCKI
EXBCLK
EXLRCK
SDTO
BCLK
LRCK
SDTI
1fs
32fs, 64fs
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK pin)
相關(guān)PDF資料
PDF描述
AK5701KN 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
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AK5701KN 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
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AK5701VN 制造商:AKM 制造商全稱:AKM 功能描述:PLL & MIC-AMP 16-Bit Stereo ADC
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