參數(shù)資料
型號(hào): AK5700VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述: 16位ツヒ單聲道ADC,帶鎖相環(huán)
文件頁(yè)數(shù): 28/61頁(yè)
文件大小: 519K
代理商: AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 28 -
Bypass Mode
When THR bit = “1”, M/S bit = “0” and PMADC bit = “0” input clocks and data of EXLRCK, EXBCLK and EXSDTI
pins are bypassed to LRCK, BCLK and SDTO pins, respectively.
When THR bit = “1”, M/S bit = “0” and PMADC bit = “1” input clocks of EXLRCK and EXBCLK pins are bypassed to
LRCK and BCLK pins, and ADC data is output from SDTO pin.
THR bit
M/S bit
PMADC bit
BCLK/LRCK
0
“L”
0
1
“L”
0
Output
1
1
Output
0
EXBCLK/EXLRCK
0
1
EXBCLK/EXLRCK
0
N/A
1
1
Output
Table 14. Bypass Mode Select
AK5700
DSP or
μ
P
32fs
SDTO
“L”
ADC data
“L”
ADC data
EXSDTI
ADC data
N/A
ADC data
Mode
Figure
Figure 24
Figure 25
Default
Power down
Slave mode
Power down
Master mode
Bypass mode
Slave & Bypass
N/A
Master mode
0
1
BCLK
LRCK
SDTI
LRCK
SDTO
1fs
BCLK
DSP or
μ
P
LRCK
SDTO
1fs
BCLK
32fs
EXBCLK
EXLRCK
EXSDTI
Figure 24. Bypass Mode
AK5700
DSP or
μ
P
BCLK
LRCK
SDTI
LRCK
SDTO
1fs
BCLK
32fs
DSP or
μ
P
LRCK
Analog In
1fs
BCLK
32fs
EXBCLK
EXLRCK
AIN
Figure 25. Slave & Bypass Mode
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