參數(shù)資料
型號(hào)： AK5700VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述： 16位ツヒ單聲道ADC，帶鎖相環(huán)
文件頁(yè)數(shù)： 56/61頁(yè)
文件大?。?/td> 519K
代理商： AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 56 -
MIC Input Recording
FS3-0 bits
(Addr:15H, D3-0)
MIC Control
(Addr:12H, D4
& Addr:13H, D1-0)
Timer Control
(Addr:1AH)
PMADC bit
(Addr:10H, D0)
ADC Internal
State
1111
X,XXX
0, 01
1, 01
Power Down
Initialize Normal State Power Down
3088 / fs
(1)
(2)
(6)
ALC State
ALC Enable
ALC Disable
ALC Disable
XXH
0AH
(3)
ALC Control 1
(Addr:1BH)
XXH
E1H
(4)
(7)
(5)
ALC Control 2
(Addr:1CH)
XXH
81H
01H
(8)
Example:
PLL Master Mode
Audio I/F Format:I2S
Sampling Frequency:44.1kHz
Pre MIC AMP:+15dB
MIC Power On
ALC setting:Refer to Figrure 37
ALC bit = “1”
(2) Addr:12H, Data:10H
Addr:13H, Data:01H
(3) Addr:1AH, Data:0AH
(1) Addr:15H, Data:2FH
(4) Addr:1BH, Data:E1H
(6) Addr:10H, Data:05H
Recording
(7) Addr:10H, Data:04H
(5) Addr:1CH, Data:81H
(8) Addr:1CH, Data:01H
Figure 48. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure 35. Registers set-up sequence at ALC operation”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK5700 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up MIC input (Addr: 12H&13H)
(3) Set up Timer Select for ALC (Addr: 1AH)
(4) Set up REF value for ALC (Addr: 1BH)
(5) Set up LMTH1-0, RGAIN1-0, LMAT1-0 and ALC bits (Addr: 1CH)
(6) Power Up MIC and ADC: PMADC bit = “0”
→
“1”
The initialization cycle time of ADC is 3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = “00”.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (0dB).
To start the recording within 100ms, the following sequence is required.
(6a) PMVCM=PMMP bits = “1”.
(6b) Wait for 2ms, then PMPLL bit = “1”.
(6c) Wait for 6ms, then PMADC bit = “1”.
(7) Power Down MIC and ADC: PMADC bit = “1”
→
“0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK5700 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADC bit = “0”). IVOL gain is not reset when PMADC = “0”,
and then IVOL operation starts from the setting value when PMADC bit is changed to “1”.
(8) ALC Disable: ALC bit = “1”
→
“0”
相關(guān)PDF資料
PDF描述
AK5701KN 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
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AK5702 4-Channel ADC with PLL & MIC-AMP
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