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參數(shù)資料
| 型號(hào)： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 21/61頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AK5700VN |
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ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 21 -
OPERATION OVERVIEW
System Clock
There are the following five clock modes to interface with external devices (see Table 1 and Table 2.)
Mode
PLL Master Mode (Note 22)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: EXLRCK or EXBCLK pin)
EXT Slave Mode
EXT Master Mode (Note 23)
Note 22. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Note 23. In case of EXT Master Mode, the register should be set as Figure 45.
Table 1. Clock Mode Setting (x: Don’t care)
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See Table 4
Figure
Figure 19
1
0
See Table 4
Figure 20
1
0
See Table 4
Figure 21
0
0
0
0
x
x
Figure 22
Figure 23
Mode
MCKO bit
MCKO pin
MCKI pin
BCLK pin,
EXBCLK pin
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin,
EXLRCK pin
0
“L”
PLL Master Mode
1
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
Selected by
PLL3-0 bits
LRCK pin
(1fs)
0
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
1
Selected by
PLL3-0 bits
EXBCLK pin
(
≥
32fs)
EXLRCK pin
(1fs)
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
0
“L”
GND
EXBCLK pin
(Selected by
PLL3-0 bits)
EXBCLK pin
(
≥
32fs)
BCLK pin
(Selected by
BCKO1-0 bits)
EXLRCK pin
(1fs)
EXT Slave Mode
0
“L”
Selected by
FS1-0 bits
EXLRCK pin
(1fs)
EXT Master Mode
0
“L”
Selected by
FS1-0 bits
LRCK pin
(1fs)
Table 2. Clock pins state in Clock Mode
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5700 is power-down mode (PDN pin = “L”) and exits reset state, the AK5700 is slave mode. After exiting reset state,
the AK5700 goes to master mode by changing M/S bit = “1”.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Salve Mode
Used pins
Default
EXBCLK, EXLRCK
BCLK, LRCK
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