- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385095 > AK5700VN (Asahi Kasei Microsystems Co.,Ltd) 16-Bit ツヒ Mono ADC with PLL & MIC-AMP PDF資料下載
參數(shù)資料
| 型號(hào)： | AK5700VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Mono ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ單聲道ADC，帶鎖相環(huán) |
| 文件頁數(shù)： | 29/61頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AK5700VN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 29 -
Audio Interface Format
Fore types of data format are available and are selected by setting the DIF1-0 bits (see Table 15). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK,
BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and SDTO pins are used in slave mode. In modes
2 and 3, the SDTO is clocked out on the falling edge (“
↓
”) of BCLK/EXBCLK. SDTO pin outputs same data two times in
one period of EXLRCK/LRCK.
Mode
DIF1 bit
DIF0 bit
SDTO
0
0
0
DSP Mode 0
1
0
1
Reserved
2
1
0
MSB justified
3
1
1
I
2
S compatible
Table 15. Audio Interface Format
In Mode 0 (DSP mode 0), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“
↑
”) of BCLK/EXBCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“
↓
”) of BCLK/EXBCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK.
DIF1
DIF0
MSBS
BCKP
MSB of SDTO is output by the rising edge (“
↑
”) of the first BCLK/EXBCLK
after the rising edge (“
↑
”) of LRCK/EXLRCK (Figure 26).
MSB of SDTO is output by the falling edge (“
↓
”) of the first
BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK (Figure 27).
MSB of SDTO is output by next rising edge (“
↑
”) of the falling edge (“
↓
”) of
the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(Figure 28).
MSB of SDTO is output by next falling edge (“
↓
”) of the rising edge (“
↑
”) of
the first BCLK/EXBCLK after the rising edge (“
↑
”) of LRCK/EXLRCK
(Figure 29).
Table 16. Audio Interface Format in Mode 0
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “
1” at 16bit data is converted to “
1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “
1” at 8-bit data will be converted to “
256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
BCLK, EXBCLK
32fs
-
≥
32fs
≥
32fs
Figure
See Table 16
-
Figure 30
Figure 31
Default
Audio Interface Format
0
0
0
1
1
0
0
0
1
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5701KN | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701_07 | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701VN | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701 | digital audio 16bit A/D converter |
| AK5702 | 4-Channel ADC with PLL & MIC-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5701 | 制造商:AKM 制造商全稱:AKM 功能描述:digital audio 16bit A/D converter |
| AK5701_07 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701KN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| AK5701KNP-L | 制造商:AKM Semiconductor Inc 功能描述:AK5701KNP-L |
| AK5701VN | 制造商:AKM 制造商全稱:AKM 功能描述:PLL & MIC-AMP 16-Bit Stereo ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。