參數(shù)資料
型號(hào): AK5700VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Mono ADC with PLL & MIC-AMP
中文描述: 16位ツヒ單聲道ADC,帶鎖相環(huán)
文件頁(yè)數(shù): 26/61頁(yè)
文件大?。?/td> 519K
代理商: AK5700VN
ASAHI KASEI
[AK5700]
MS0569-E-01
2006/12
- 26 -
EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK5700 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit
is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), EXLRCK (fs) and EXBCLK (
32fs). The master clock (MCKI) should be synchronized with
EXLRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see
Table 11).
Mode
FS3-2 bits
FS1 bit
FS0 bit
MCKI Input
Frequency
256fs
1024fs
512fs
256fs
Sampling Frequency
Range
7.35kHz
48kHz
7.35kHz
13kHz
7.35kHz
26kHz
7.35kHz
48kHz
0
1
2
3
Don’t care
Don’t care
Don’t care
Don’t care
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
0
0
1
1
0
1
0
1
Default
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation
(PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
should be in the power-down mode (PMADC bit = “0”).
AK5700
DSP or
μ
P
MCKI
EXBCLK
EXLRCK
SDTO
BCLK
LRCK
SDTI
MCKO
1fs
32fs
MCLK
256fs, 512fs or 1024fs
Figure 22. EXT Slave Mode
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