
TM1300 Data Book
Philips Semiconductors
12-8
PRODUCT SPECIFICATION
andaTSU for TM1300 less or equal than 0.4 ns. In other
words the following equation needs to be met:
.
Where TCS is the skew between MM_CLK0 and
MM_CLK1, and TSU the input data setup time as defined
in Section 1.9.4.7 on page 1-15.
12.16.1 Main AC Parameter requirements
The TM1300 SDRAM interface was designed to support
a wide range of SDRAM vendors. Table 12-13 describes
some of the minimum SDRAM AC requirements for
TM1300 to operate correctly. The symbols or names are
not really standardized and may differ from one vendor
to another one. The table is not meant to be exhaustive
and shows only the main parameters. Parameters are
expressed in clock cycles rather than ns.
12.17 EXAMPLE BLOCK DIAGRAMS
Figures 112-5 through 12-10 illustrate some of the pos-
sible memory configurations that can be built with
TM1300. For all the following schemes MM_A[12:11]
when used as bank addresses, are interchangeable (i.e.
it does not matter whether one is connected to Bank 1 or
Bank 0.).
12.17.1 16-Mbit Devices or Less
These devices allow small memory configurations to be
built. They are described in the TM1000 and TM1100 da-
tabooks. Figure 12-5 shows a 4-MB memory system.
12.17.2 64-Mbit Devices
64-Mbit SDRAMs organized in x16 can be used to build
a 16-, 32-, 48- or 64-MB memory systems. Figure 12-6
Table 12-13. Minimum AC Parameters
Description
Symbol Clocks
ACTIVE command period
tRC
10
ACTIVE to PRECHARGE command
tRAS
7
PRECHARGE command period
tRP
3
T
cycle
t
AC
T
board
T
CS
T
SU
++
+
≥
ACTIVE Bank A to ACTIVE bank B
tRRD
3
ACTIVE to READ or WRITE command
tRCD
3
WRITE recovery time
tWR
2
Table 12-13. Minimum AC Parameters
Description
Symbol Clocks
Figure 12-5. Schematic of a 4-MB memory system consisting of two 2
×512K×16 SDRAM chips (one rank).
DQ[15:0]
UDQM
CLK
Address
Control
LDQM
CS#
2
×512K×16
SDRAM
MM_CS#[0]
MM_A[11:0]
MM_CLK[1:0]
MM_DQ[31:0]
MM_DQM[3:0]
MM_CS#[0]
MM_CLK[1]
MM_DQM[2]
MM_DQM[3]
MM_DQ[31:16]
DQ[15:0]
UDQM
CLK
Address
Control
LDQM
CS#
2
×512K×16
SDRAM
MM_DQM[0]
MM_DQM[1]
MM_DQ[15:0]
MM_CS#[0]
MM_CLK[0]
33
TM1300
MM_RAS,
CAS,
WE#,
CKE