
TM1300 Data Book
Philips Semiconductors
A-60
PRODUCT SPECIFICATION
IEEE status ags from oating-point square root
SYNTAX
[ IF r
guard ] fsqrtflags rsrc1
→ rdest
FUNCTION
if r
guard then
r
dest
← ieee_ags(square_root((oat)rsrc1))
ATTRIBUTES
Function unit
ftough
Operation code
111
Number of operands
1
Modier
No
Modier range
—
Latency
17
Recovery
16
Issue slots
2
DESCRIPTION
The fsqrtflags operation computes the IEEE exceptions that would result from computing the squareroot of
r
src1 and stores a bit vector representing the exception ags into rdest. The argument value is in IEEE single-
precision oating-point format; the result is an integer bit vector. The bit vector stored in r
dest has the same format as
the IEEE exception bits in the PCSW. The exception ags in PCSW are left unchanged by this operation. Rounding is
according to the IEEE rounding mode bits in PCSW. If the argument is denormalized, zero is substituted before
computing the squareroot, and the IFZ bit in the result is set. If the result is denormalized, and the OFZ ag in the
PCSW is set.
The fsqrtflags operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0)
fsqrtflags r60
→ r90
r90
← 0x10 (INV)
r40 = 0x40400000 (3.0)
fsqrtflags r40
→ r95
r95
← 0x2 (INX)
r10 = 0, r40 = 0x40400000 (3.0)
IF r10 fsqrtflags r40
→ r100
no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0)
IF r20 fsqrtflags r40
→ r110
r110
← 0x2 (INX)
r82 = 0x00c00000 (1.763241526e–38)
fsqrtflags r82
→ r112
r112
← 0x2 (INX)
r84 = 0x7f800000 (+INF)
fsqrtflags r84
→ r113
r113
← 0
r70 = 0x7f7fffff (3.402823466e+38)
fsqrtflags r70
→ r120
r120
← 0x2 (INX)
r80 = 0x00400000 (5.877471754e-39)
fsqrtflags r80
→ r125
r125
← 0x20 (IFZ)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
31
00
SEE ALSO
fsqrt readpcsw
fsqrtflags