
Philips Semiconductors
Enhanced Video Out
PRODUCT SPECIFICATION
7-9
data interpretation is done, and data is transferred at the
rate of one byte per VO_CLK. Data is clocked out on the
positive edge of VO_CLK.
When
data-streaming
mode
is
enabled
and
EVO_ENABLE = 1 and SYNC_STREAMING = 1, the
VO_IO2 signal indicates a data-valid condition. This sig-
nal is asserted when the EVO starts outputting valid data
(that is, data-streaming mode is enabled and video out is
running), and is de-asserted when data-streaming mode
is disabled. As shown in Figure 7-17, the data-valid sig-
nal on VO_IO2 is asserted just before the first valid byte
is present on VO_DATA[7:0], and is de-asserted just af-
ter the last valid byte was sent, or if an HBE error is sig-
naled. All transitions of VO_IO2 occur on the rising edge
of VO_CLK. The VO_IO1 signal generates a pulse one
VO_CLK cycle before the first valid data is sent. The
transitions of VO_IO1 occur on the rising edge of
VO_CLK and last for one VO_CLK cycle.
In message-passing mode, the EVO issues signals on
VO_IO1 and VO_IO2 to indicate the start and end of
messages.
When
message
passing
is
started
by
setting
VO_CTL.VO_ENABLE, the EVO sends a Start condition
on VO_IO1. When the EVO has transferred the contents
of the buffer, it sends an End condition on VO_IO2, sets
BFR1_EMPTY, and interrupts the DSPCPU. The EVO
stops, and no further operation takes place until the
DSPCPU sets VO_ENABLE again to start another mes-
sage, or until the DSCPU initiates other EVO operation.
The timing for these signals is shown in Figure 7-18.
7.12
IMAGE DATA MEMORY FORMATS
7.12.1
Video Image Formats
The EVO accepts memory-resident video image data in
three formats: YUV 4:2:2 co-sited, YUV 4:2:2 inter-
spersed, and YUV 4:2:0. These formats are shown in
Figure 7-19 through Figure 7-21.
7.12.2
Planar Storage of Video Image Data in
Memory
Video image data is stored in memory with one table for
each of the Y, U and V components. This is called planar
format. This is shown in Figure 7-22 for YUV 4:2:2 image
data. The EVO merges bytes from each of the three ta-
EAV
Image Data
EAV
Line 525/625
One Frame
VO_IO2
Delay SLAVE_DLY in VO_CLK cycles
Line 1
Line 2
Line FRAME_PRESET
Line 525/625
Line 1
EAV
Line counter loaded by FRAME_PRESET
Figure 7-16. Genlock mode.
VO_DATA[7:0]
VO_IO2
VO_IO1
VO_CLK
XX
D0
D1
D2
D3
D4
D5
Dk
XX
DATA_VALID
Figure 7-17. Data-streaming valid data signals.
VO_DATA[7:0]
VO_IO1
VO_IO2
VO_CLK
XX
D0
D1
D2
D3
D4
D5
D6
D7
XX
Start of
message
End of
message
Figure 7-18. Message-passing START and END signals.