
TM1300 Data Book
Philips Semiconductors
A-144
PRODUCT SPECIFICATION
pref16x
prefetch with 16-bit scaled index
SYNTAX
[ IF r
guard ] pref16x rsrc1 rsrc2
FUNCTION
if r
guard then {
cache_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + (2 x rscr2)) & cache_block_mask]
}
ATTRIBUTES
Function unit
dmemspec
Operation code
211
Number of operands
2
Modier
No
Modier range
-
Latency
-
Issue slots
5
DESCRIPTION
The pref16x operation loads one full cache block from the main memory at the address computed by ((rsrc1+ (2 x
rscr2)) & cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be
executed. The prefetch unit will not execute this operation when the data to be prefetched is already in the data cache.
The data cache has hardware to simultaneously sustain two cache misses or prefetches. A pref16x operation will not
be executed when the cache is already occupied with 2 cache misses, when the operation is issued.
The pref16x operation optionally takes a guard, specied in rguard. If a guard is present, its LSB controls the
execution of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not
executed
EXAMPLES
NOTE: This operation is supported only in TM1000, TM1100 and TM1300 and it is not
guaranteed to be available in future generations of Trimedia products.
Initial Values
Operation
Result
r10 = 0xabcd, r12 = 0xc
cache_block_size = 0x40
pref16x r10 r12
Loads a cache line for the address space from
0xabc0 to 0xabff from the main memory. If the data is
already in the cache, the operation is not executed.
r10 = 0xabcd, r11 = 0, r12=0xc,
cache_block_size = 0x40
IF r11 pref16x r10 r12
since guard is false, pref16x operation is not executed
r10 = 0xabff, r11 = 1, r12 =0x1,
cache_block_size = 0x40
IF r11 pref16x r10 r12
Loads a cache line for the address space from
0xac00 to 0x0xac3f from the main memory. If the
data is already in the cache, the operation is not exe-
cuted.
SEE ALSO
pref32x prefd prefr allocd
allocr allocx