
Philips Semiconductors
DSPCPU Architecture
PRODUCT SPECIFICATION
3-13
the counter will have to loop around before an interrupt is
generated.
A modulus value of zero causes a wrap-around as if the
modulus value was 232.
On RESET, the TCTL registers are cleared, and the val-
ue of the TMODULUS and TVALUE registers is unde-
fined.
3.9
DEBUG SUPPORT
This section describes the special debug support offered
by the DSPCPU. Instruction and data breakpoints can be
defined through a set of registers in the MMIO register
space. When a breakpoint is matched, an event is gen-
erated that can be used as a timer source (see Section
3.8, “Timers”). The timer TMODULUS has to be set to
generate a DSPCPU interrupt after the desired number
of breakpoint matches.
3.9.1
Instruction Breakpoints
The instruction-breakpoint control register is shown in
Figure 3-11. On RESET, the BICTL register is cleared.
(MMIO-register addresses shown are offset with respect
to MMIO_BASE.)
The instruction-breakpoint address-range registers are
shown in Figure 3-12. After RESET, the value of these
registers is undefined. (MMIO-register addresses shown
are offset with respect to MMIO_BASE.)
When the IC bit in the breakpoint control register is set to
‘1’, instruction breakpoints are activated. Any instruction
address issued by the TM1300 chip is compared against
the low and high address-range values. The IAC bit in
the breakpoint control register determines whether the
instruction address needs to be inside or outside of the
range defined by the low and high address-range regis-
ters. A successful comparison takes place when either:
IAC = ‘0’ and low
≤ iaddr ≤ high, or
IAC = ‘1’ and iaddr < low or iaddr > high.
On a successful comparison, an instruction breakpoint
event is generated, which can be used as a clock input
to a timer. After counting the programmed number of in-
struction breakpoint events, the timer will generate an in-
terrupt request.
Table 3-11. Timer base MMIO address
TIMER1
MMIO_BASE+0x10,0C00
TIMER2
MMIO_BASE+0x10,0C20
TIMER3
MMIO_BASE+0x10,0C40
SYSTIMER
MMIO_BASE+0x10,0C60
Table 3-12. Timer source selections
Source Name
Source
Bits
Value
Source Description
CLOCK
0
CPU clock
PRESCALE
1
prescaled CPU clock
TRI_TIMER_CLK
2
external clock pin
DATABREAK
3
data breakpoints
INSTBREAK
4
instruction breakpoints
CACHE1
5
cache event 1
CACHE2
6
cache event 2
VI_CLK
7
video in clock pin
VO_CLK
8
video out clock pin
AI_WS
9
audio in word strobe pin
AO_WS
10
audio out word strobe pin
SSI_RXFSX
11
SSI receive frame sync pin
SSI_IO2
12
SSI transmit frame sync pin
—
13-15
undened
MODULUS
TMODULUS (r/w)
0
31
0
Timer base offset:
TVALUE (r/w)
4
TCTL (r/w)
8
3
7
11
15
19
23
27
“PRESCALE”:
Prescale value is
2^PRESCALE, i.e.,
in the range [1..32768]
“SOURCE” select:
see table Table 3-12
VALUE
PRESCALE
SOURCE
“RUN” bit:
0
Timer stopped
1
Timer running
R
Figure 3-10. Timer register definitions.
31
0
MMIO_BASE
offset:
BICTL (r/w)
0x10 1000
3
7
11
15
19
23
27
‘IAC’ Instruction address control:
0
Breakpoint if address inside range
1
Breakpoint if address outside range
‘IC’ Instruction control bit:
0 Disable instruction breakpoints
1 Enable instruction breakpoints
IC
Figure 3-11. Instruction-breakpoint control register.