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| 型號(hào)： | 935266871557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA292 |
| 封裝： | PLASTIC, SOT-553-1, BGA-292 |
| 文件頁(yè)數(shù)： | 490/532頁(yè) |
| 文件大?。?/td> | 1895K |
| 代理商： | 935266871557 |
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TM1300 Data Book
Philips Semiconductors
3-10
PRODUCT SPECIFICATION
Programmer’s note: See the Philips TriMedia Cookbook
(Book 2 of TriMedia SDE documentation) for information
on writing interrupt handlers.
3.5.3.2
Interrupt modes
DSPCPU interrupt sources can be programmed to oper-
ate in either
level-sensitive or edge-triggered mode. Op-
eration in edge-triggered or level-sensitive mode is de-
termined by a bit in the ISETTING MMIO locations
corresponding to the source, as defined in Figure 3-7.
On RESET, all ISETTING registers are cleared.
In edge-triggered mode, the leading edge of the signal
on the device interrupt request line causes the VIC (Vec-
tored Interrupt Controller) to set the
interrupt pending flag
corresponding to the device source number. Note that,
for active high signals, the leading edge is the positive
edge, whereas for active low request signals (such as
PCI INTA#), the negative edge is the leading edge. The
interrupt remains pending until one of two events occurs:
The VIC successfully dispatches the vector corre-
sponding to the source to the TM1300 CPU, or
TM1300 CPU software clears the interrupt-pending
ag by a direct write to the ICLEAR location.
No interrupt acknowledge to ICLEAR is needed for de-
vices operating in edge-triggered mode, since the vector
dispatch clears the IPENDING request. The device itself
may however need a device-specific interrupt acknowl-
edge to clear the requesting condition. Edge-triggered
mode is
not recommended for devices that can signal
multiple simultaneous interrupt conditions. The on-chip
timers
must be operated in edge triggered mode.
In level-sensitive mode, the device requests an interrupt
by asserting the VIC source request line. The device
holds the request until the device interrupt handler per-
forms a device interrupt acknowledge. It is
highly recom-
mended that all off-chip and on-chip sources, with the ex-
ception of the timers, operate in level-sensitive mode.
3.5.3.3
Device interrupt acknowledge
All devices capable of generating level-triggered inter-
rupts have interrupt acknowledge bits in their memory
mapped control registers for this purpose. An interrupt
acknowledge is performed by a store to such control reg-
ister, with a ‘1’ in the bit position(s) corresponding to the
desired acknowledge flags.
Programmers note: the store operation that performs the
interrupt acknowledge should be issued at least 2 cycles
before the (interruptible) jump that ends an interrupt han-
dler. This ensures that the same interrupt is not dis-
patched twice due to request de-assertion clock delays.
3.5.3.4
Interrupt priorities
Each interrupt source can be programmed to request
one out of eight levels of priorities. The highest priority
level (level 7) corresponds to requesting an NMI—an in-
terrupt that cannot be masked by the DSPCPU PC-
SW.IEN bit. The other levels request regular interrupts,
that can be masked as a group by the PCSW.IEN flag.
Level six represents the highest priority normal interrupt
level and level zero represents the lowest. Refer to
Figure 3-7 for details of programming the priority level.
The VIC arbitrates the highest-priority pending interrupt
requestor. Sources programmed to request at the same
level are treated with a fixed priority, from source number
0 (highest) to 31 (lowest). At such time as the DSPCPU
is willing to process special events, the vector of highest
priority NMI source will be dispatched. If no NMI is pend-
ing, and the DSPCPU allows regular interrupts (PC-
SW.IEN is asserted), the vector of the highest priority
regular source is dispatched. Once a vector is dis-
patched, the corresponding interrupt pending flag is de-
asserted (edge triggered mode sources only).
3.5.3.5
Interrupt masking
A single MMIO register (IMASK in Figure 3-8) allows
masking of an arbitrary subset of the interrupt sources.
Masking applies to both regular as well as NMI level re-
questors. Masking is used by software to disable unused
devices and/or to implement nested interrupt handling. In
the latter case, each interrupt handler can stack the old
IMASK content for later restoration and insert a new
mask that only allows the interrupts it is willing to handle.
For level-triggered device handlers, IMASK should also
exclude the device itself to prevent repeated handler ac-
tivation.
Each interrupt source device typically has its own inter-
rupt enable flag(s) that determine whether certain key
MP31
ISETTING3 (r/w)
0x10 081C
31
0
MMIO_BASE
offset:
ISETTING2 (r/w)
0x10 0818
ISETTING1 (r/w)
0x10 0814
ISETTING0 (r/w)
0x10 0810
MP30
MP29
MP28
MP27
MP26
MP25
MP24
3
7
11
15
19
23
27
Each MP Field:
0xxx
source operates in edge-triggered mode
1xxx
source operates in level-sensitive mode
Each MP Field:
x111
NMI (highest) priority
x110
maskable level 6
...
x000
maskable level 0
MP23
MP22
MP21
MP20
MP19
MP18
MP17
MP16
MP15
MP14
MP13
MP12
MP11
MP10
MP9
MP8
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
Figure 3-7. Interrupt mode and priority MMIO locations and formats.
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