
TM1300 Data Book
Philips Semiconductors
A-62
PRODUCT SPECIFICATION
IEEE status ags from oating-point subtract
SYNTAX
[ IF r
guard ] fsubflags rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then
r
dest
← ieee_ags((oat)rsrc1 – (oat)rsrc2)
ATTRIBUTES
Function unit
falu
Operation code
114
Number of operands
2
Modier
No
Modier range
—
Latency
3
Issue slots
1, 4
DESCRIPTION
The fsubflags operation computes the IEEE exceptions that would result from computing the difference r
src1–
r
src2 and writes a bit vector representing the exception ags into rdest. The argument values are in IEEE single-
precision oating-point format; the result is an integer bit vector. The bit vector stored in r
dest has the same format as
the IEEE exception bits in the PCSW. The exception ags in PCSW are left unchanged by this operation. Rounding is
according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted before
computing the difference, and the IFZ bit in the result is set. If the difference would be denormalized, the OFZ bit in the
result is set.
The fsubflags operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r60 = 0xc0400000 (–3.0),
r30 = 0x3f800000 (1.0)
fsubflags r60 r30
→ r90
r90
← 0
r40 = 0x40400000 (3.0),
r60 = 0xc0400000 (–3.0)
fsubflags r40 r60
→ r95
r95
← 0
r10 = 0, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
IF r10 fsubflags r40 r80
→ r100 no change, since guard is false
r20 = 1, r40 = 0x40400000 (3.0),
r80 = 0x00800000 (1.17549435e-38)
IF r20 fsubflags r40 r80
→ r110 r110 ← 0x2 (INX)
r40 = 0x40400000 (3.0),
r81 = 0x00400000 (5.877471754e–39)
fsubflags r40 r81
→ r111
r111
← 0x20 (IFZ)
r82 = 0x00c00000 (1.763241526e-38),
r83 = 0x0080000 (1.175494351e-38)
fsubflags r82 r83
→ r112
r112
← 0x40 (OFZ)
r84 = 0x7f800000 (+INF),
r85 = 0x7f800000 (+INF)
fsubflags r84 r85
→ r113
r113
← 0x10 (INV)
r70 = 0x7f7fffff (3.402823466e+38)
r86 = 0xff7fffff (-3.402823466e+38)
fsubflags r70 r86
→ r120
r120
← 0xA (OVF,INX)
r87 = 0xffffffff (QNaN))
r30 = 0x3f800000 (1.0
fsubflags r87 r30
→ r125
r125
← 0x0
r87 = 0xffbfffff (SNaN))
r30 = 0x3f800000 (1.0
fsubflags r87 r30
→ r125
r125
← 0x10 (INV)
r83 = 0x0080001 (1.175494421e-38),
r89 = 0x0080000 (1.175494351e-38)
fsubflags r83 r89
→ r126
r126
← 0x4 (UNF)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
31
00
SEE ALSO
fsub faddflags readpcsw
fsubflags