
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-9
Arithmetic shift right
SYNTAX
[ IF r
guard ] asr rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then {
n
← rsrc2<4:0>
r
dest<31:31–n>
← rsrc1<31>
r
dest<30–n:0>
← rsrc1<30:n>
if rsrc2<31:5> != 0 {
rdest <- rsrc1<31>
}
}
ATTRIBUTES
Function unit
shifter
Operation code
18
Number of operands
2
Modier
No
Modier range
—
Latency
1
Issue slots
1, 2
DESCRIPTION
As shown below, the asr operation takes two arguments, r
src1 and rsrc2.Rsrc2 species an unsigned shift amount,
and r
src1 is arithmetically shifted right by this amount. If the rsrc2<31:5> value is not zero, then take this as a shift by
32 or more bits. The MSB (sign bit) of r
src1 is replicated as needed to ll vacated bits from the left.
The asr operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x7008000f, r20 = 1
asr r30 r20
→ r50
r50
← 0x38040007
r30 = 0x7008000f, r42 = 2
asr r30 r42
→ r60
r60
← 0x1c020003
r10 = 0, r30 = 0x7008000f, r44 = 4
IF r10 asr r30 r44
→ r70
no change, since guard is false
r20 = 1, r30 = 0x7008000f, r44 = 4
IF r20 asr r30 r44
→ r80
r80
← 0x07008000
r40 = 0x80030007, r44 = 4
asr r40 r44
→ r90
r90
← 0xf8003000
r30 = 0x7008000f, r45 = 0x1f
asr r30 r45
→ r100
r100
← 0x00000000
r30 = 0x8008000f, r45 = 0x1f
asr r30 r45
→ r100
r100
← 0xffffffff
r30 = 0x7008000f, r45 = 0x20
asr r30 r45
→ r100
r100
← 0x00000000
r30 = 0x8008000f, r45 = 0x20
asr r30 r45
→ r100
r100
← 0xffffffff
r30 = 0x8008000f, r45 = 0x23
asr r30 r45
→ r100
r100
← 0xffffffff
0
31
r
src1
0
r
src2
S
Right shifter
32 bits from r
src1
0
3
r
dest
2
S
Intermediate result
(example:
n = 3)
r
src2
S
31
SEE ALSO
asl asli asri lsl lsli lsr
lsri rol roli
asr