
Philips Semiconductors
Pin List
PRODUCT SPECIFICATION
1-17
1.9.4.13
AudioIn I/O timing
Notes:
1. See the timing measurement conditions in Figure 1-19.
2. The timing measurements are done with respect to the clock edge according to CLOCK_EDGE
3. SER_MASTER asserted, i.e. Audio In is the source of AI_WS. See the timing measurement condition in Figure 1-20.
1.9.4.14
Audio Out I/O timing
Notes:
1. See the timing measurement conditions in Figure 1-21.
2. See the timing measurement conditions in Figure 1-23.
3. The timing measurements are done with respect to the AO_SCK clock edge according to CLOCK_EDGE
4. TM-1 is the serial interface master, i.e. AO_SCK, AO_WS are outputs
5. TM-1 is serial interface slave, i.e. AO_SCK, AO_WS are inputs
6. See the timing measurement conditions in Figure 1-22.
1.9.4.15
SSI I/O timing
Notes:
1. Interrupt latency limits SSI to a practical use at a bit rate of 1.5 Mbit/sec.
2. See the timing measurement conditions in Figure 1-24.
3. See the timing measurement conditions in Figure 1-25.
Symbol
Parameter
Min.
Max
Units
Notes
fAI-SCK
Audio In AI_SCK clock frequency
22
MHz
Tsu-SCK
Input setup time to AI_SCK
3
ns
1,2
Th-SCK
Input hold time from AI_SCK
2
ns
1,2
TSCK-WS
AI_SCK to AI_WS
10
ns
3
Symbol
Parameter
Min.
Max
Units
Notes
fAO-SCK
Audio Out AO_SCK clock frequency
22
MHz
TSCK-DV
AO_SCK to AO_SDx valid
2
12
ns
1,3,4
TSCK-DV
AO_SCK to AO_SDx valid
2
12
ns
1,3,5
Tsu-SCK
Input setup time to AO_SCK
4
ns
2,3,5
Th-SCK
Input hold time from AO_SCK
2
ns
2,3,5
TSCK-WS
AO_SCK to AO_WS
10
ns
3,4,6
Symbol
Parameter
Min.
Max
Units
Notes
fSSI-CLK
SSI_CLK clock frequency
20
MHz
1
TCLK-DV
SSI_CLK to data valid
2
12
ns
2
Tsu-CLK
Input setup time to SSI_CLK
3
ns
3
Th-CLK
Input hold time from SSI_CLK
2
ns
3
Figure 1-1. STRG3, STRG5 test load circuit
12 pF
Output
Buffer
rise/fall test point
2” true length
50-ohm
30-ohm
tm1300 pin