
Philips Semiconductors
DSPCPU Operations for TM1300
PRODUCT SPECIFICATION
A-155
Read program control and status word
SYNTAX
[ IF r
guard ] readpcsw
→ rdest
FUNCTION
if r
guard then {
r
dest
← PCSW
}
ATTRIBUTES
Function unit
fcomp
Operation code
158
Number of operands
0
Modier
No
Modier range
—
Latency
1
Issue slots
3
DESCRIPTION
The readpcsw writes the current value of the PCSW (Program Control and Status Word) processor register to
r
dest. The layout of PCSW is shown below.
Fields in the PCSW have two chief purposes: to control aspects of processor operation and to record events that
occur during program execution. Thus, readpcsw can be used to determine current processor operating modes and
what events have occurred; this operation can also be used to save state before idling a task in a multi-tasking
environment.
The readpcsw operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
Initial Values
Operation
Result
PCSW = 0x80110642
readpcsw
→ r100
r100
← 0x80110642 (trap on MSE, INV and DBZ
enabled, IEN=1 - interrupts enabled, BSX=1 - little
endian mode of operation, OFZ=1 - a denormalized
result was produced somewhere, INX=1 - an inexact
result was produced somewhere)
r20 = 0, PCSW = 0x80000000
IF r20 readpcsw
→ r101
no change, since guard is false
r21 = 1, PCSW = 0x80000000
IF r21 readpcsw
→ r102
r102
← 0x80000000 (trap on MSE enabled)
MSE
CS
IEN
BSX
IEEE MODE
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
Misaligned store exception
Count stalls (1
Yes)
FP exception trap-enable bits
IEEE rounding mode
0
to nearest, 1 to zero, 2 to positive, 3 to negative
Interrupt enable (1
allow interrupts)
Byte sex (1
little endian)
PCSW<31:16>
PCSW<15:0>
UNDEF
Misaligned store
exception trap enable
Trap on first exit
FP exceptions
TRP
MSE
TFE
TRP
OFZ
TRP
IFZ
TRP
INV
TRP
OVF
TRP
UNF
TRP
INX
TRP
DBZ
16
17
18
19
20
21
22
23
25
26
27
28
30
31
UNDEF
UNDEFINED
13
WBE
RSE
Write back error
Reserved exception
TRP
WBE
TRP
RSE
Write back error trap enable
Reserved exception
trap enable
29
SEE ALSO
writepcsw
readpcsw