參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 83/97頁
文件大小： 1885K
代理商： 7640
82
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.3 ELECTRICAL CHARACTERISTICS
Table 2.3. Electrical Characteristics (Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85 C unless otherwise noted)
Symbol
Parameters
Test Conditions
Limits
Unit
Min Typ. Max
V
OH
H output
voltage
P0, P1, P2, P3, P4, P5, P6, P7, P8
Ioh = -10mA
V
CC
-
2.0
V
V
OH
H output
voltage
USB D+, D-
USB D+, USB D- pins pull down to Vss by 15
K
± 5
% and USB D+ pin pull up to ExtCap
pin by 1.5 K
±
5%
V
OL
L output
voltage
P0, P1, P2, P3, P4, P5, P6, P7, P8
Iol = 10mA
2.0
V
V
OL
L output
voltage
USB D+, D-
USB D+, USB D- pins pull down to Vss by 15
K
± 5
% and USB D+ pin pull up to ExtCap
pin by 1.5 K
±
5%
V
T
+
~V
T
-
Hysteresis
CNTR0, CNTR1, INT0, INT1, RDY,
HOLD, P2
URXD1, URXD2 (SCLK),
CTS2
(SRXD),
SRD
Y,
CTS1
0.5
V
0.5
V
RESET
P0, P1, P2, P3, P4, P5, P6, P7, P8
0.5
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
I
IH
H input current
V
i
= V
CC
5
RESET, USB D+, USB D-, CNV
SS
X
in
XC
in
P0, P1, P3, P4, P5, P6, P7, P8
5
9
20
5
I
IL
L input current
V
i
= V
SS
V
i
= V
SS
(Pullups off)
V
CC
= 5V, V
i
= V
SS
(Pullups on)
-5
P2
-5
-30
-75
-140
RESET, USB D+, USB D-
CNV
SS
X
in
XC
in
V
i
= V
SS
-5
-20
-9
-20
μ
A
μ
A
-5
V
RAM
RAM
retention
voltage
Clocks stopped
2.0
V
I
CC
Supply current
(Output
transistors are
isolated)
Normal Mode
f(X
) = 24MHz,
Φ
= 12MHz,
USB operating, frequency synthesizer on,
Note 1
f(X
) = 24MHz,
Φ
= 12MHz,
USB suspended, frequency synthesizer on,
USB clock disabled
f(XC
in
) = 32KHz,
Φ
= 16KHz,
USB disabled, frequency synthesizer off,
transceiver voltage converter off
Note 3
Transceiver voltage converter on with USBC3
=
“
1
”
(low current mode)
T
a
= 25
°
C
, transceiver voltage converter off
T
a
= 85
°
C
, transceiver voltage converter off
Wait Mode
Note 2
7.5
10
mA
6
10
μ
A
200
250
μ
A
Stop Mode
0.1
1
μ
A
μ
A
10
2.8
3.6
0.3
5.25
70
90
mA
V
V
Note 1:
Icc test conditions
Note 2:
Icc test conditions
Note 3:
Icc test conditions
Single chip mode (run state)
Single chip mode (wait state)
Single chip mode (wait state)
Square wave clock input on X
in
(X
out
drive disabled)
Square wave clock input on X
in
(X
out
drive disabled)
X
in
/X
out
oscillation disabled
I/O pins isolated
I/O pins isolated
Square wave clock input on XC
in
(XC
out
drive disabled)
Frequency synthesizer running
Frequency synthesizer running
I/O pins isolated
USB operating with transceiver voltage converter enabled
USB in suspend state with USB clock disabled
Frequency synthesizer disabled
CPU and DMAC running
Transceiver voltage converter enabled
USB and USB clock disabled
Timers and SCSG running
Timers and SCSG running
Transceiver voltage converter disabled
BothUARTs transmitting
CPU and DMAC not running
Timers and SCSG running
MBI and SIO disabled
Both UARTs, SIO, and MBI disabled
CPU and DMAC not running
Both UARTs, SIO, and MBI disabled
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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