參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 73/97頁(yè)
文件大?。?/td> 1885K
代理商： 7640
72
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.24 OSCILLATOR CIRCUIT
An on-chip oscillator provides the system and periph-
eral clocks as well as the USB clock necessary for
operation. This oscillator circuit is comprised of ampli-
fiers that provide the gain necessary for oscillation,
oscillation control logic, a frequency synthesizer, and
buffering of the clock signals.
A Clock Control register (CCR) is shown in Figure 1.89
and a flow diagram for the oscillator circuit is shown in
Figure 1.90.
The following external clock inputs are supported:
A quartz crystal oscillator of up to 24 MHz, connected
to the X
in
and X
out
pins.
A ceramic resonator or quartz crystal oscillator of
32.768 kHz, connected to the XC
in
and XC
out
pins.
An external clock signal of up to 5.00 MHz, connected
to the XCin pin.
The frequency synthesizer can be used to generate a
48MHz clock signal (f
USB
) needed by the USB block
and clock f
SYN
, which can be chosen as the source
for the system and peripheral clocks. Both f
USB
and
f
SYN
are phase-locked frequency multiples of the fre-
quency synthesizer input. The inputs to the frequency
synthesizer can be either X
in
or XC
in
.
The two-phase non-overlapping system clock (CPU
and peripherals) is derived from the source to the
clock circuit and is half the frequency of the source.
(i.e. Source = 24 MHz, system clock = 12 MHz) Any
one of four clock signals can be chosen as the source
for the system and peripheral clocks; f(X
in
)/2, f(X
in
),
f(XC
in
), or f
SYN
. The selection is based on the values of
bits CPMA6, CPMA7 and CCR7. The default source
after reset is fXin/2.
The default source for the system and peripheral
clocks is f(X
in
)/2. If f(X
in
)= 24MHz, then the CPU will
be running at = 6MHz (low frequency mode. For the
CPU to run in high frequency mode, i.e., source of
clock = f(X
in
), write a “1” to bit 7 of the clock control
register. (If an external clock signal is input to X
in
or
XC
in
, the inverting amplifiers can be disabled by
means of the CCR6 and CCR7 bits, respectively, in or-
der to reduce power consumption).
Bits 0-4
Reserved (Read/Write “0”)
CCR5:
XC
out
Oscillation Drive Diable Bit (bit 5).
0: XC
out
oscillation drive is enabled (when XC
in
oscillation is enabled).
1: XC
oscillation drive is disabled.
X
out
Oscillation Drive Disable Bit (bit 6).
0: XC
out
oscillation drive is enabled (when XC
in
oscillation is enabled).
1: XC
oscillation drive is disabled.
X
in
Divider Select Bit (bit 7).
0: f(X
in
)/2 is used for the system clock source when CMPA 7:6=00.
1: f(X
in
) is used for the system clock source when CMPA 7:6=10.
CCR6:
CCR7:
CCR7
MSB
7
LSB
0
Address: 001F
16
Access: R/W
Reset: 00
16
Reserved
Reserved
Reserved
Reserved
Reserved
CCR6
CCR5
Fig. 1.89. Clock Control Register (CCR)
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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