參數(shù)資料
型號: 7640
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述: 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù): 42/97頁
文件大小: 1885K
代理商: 7640
41
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19 UART
This chip contains two identical UARTs. Each UART
has the following main features:
Clock selection.................................. or SCSGCLK
Prescaler selection ...............x1/x8/x32/x256 divisions
............................................(both
Baud rate .......................................... (at = 12MHz)
.........................11.4 bits/second-750 Kbytes/second
Error detection......................................parity/framing/
......................................................overrun/error sum
Parity .................................................. odd/even/none
Stop bits........................................................... 1 or 2
Character length .................................... 7, 8, or 9 bits
Transmit/receive buffer ..................................2 stages
...................................................... (double buffering)
Handshaking ...............................Clear-to-Send (CTS)
............................................. Request-to-Send (RTS)
Interrupt generation conditions............. Transmit Buffer
.....................................Empty or Transmit Complete
...........................................................Receive Buffer
....................................................Receive Error Sum
Address ............... mode for multi-receiver environment
and SCSGCLK)
The following descriptions apply to both UARTs.
The UART receives parallel data from the core or
DMAC, converts it into serial data, and transmits the
results to the send data output terminal UTXDx. The
UART receives serial data from an external source
through the receive data input URXDx, converts it into
parallel data, and makes it available to the core or
DMAC. The UART can detect parity, overrun, and
framing errors in the input stream and report the appro-
priate status information. A double buffering
configuration is used for the UART’s transmit and re-
ceive
operations.
This
accomplished by the use of a transmit buffer and
transmit shift register on the transmit side and the re-
ceive buffer and receive shift register on the receive
side.
The UART supports an address mode for use in a
multi-receiver environment where an address is sent
before each message to designate which UART or
UARTs are to wake-up and receive the message. Fig-
ure 1.41 is a block diagram of the UART. It is valid for
both UART1 and UART2.
double
buffering
is
Fig. 1.41. UART Block Diagram
URegister
UxMOD
UART Control
UxCON
Shift Register
Data Bus
Transmit
UART Status
UxSTS
Data Bus
Generator
BReceive
StoDetect
Bit Counter
LE 1,0; PEN; STB
Bit Counter
/1/8/32/256
Clock Set
Tx Enable
Tx Buffer Empty
TBE
TIS = "0"
TIS = "1"
TCM
Transmit line to UTXDx
Receive line from URXDx
Receive Buffer Full Interrupt
Receive Error Interrupt
Rx Complete
Rx Status Errors
Tx Complete
LE 1,0; PEN; STB
PS 1,0
CLKSEL
Φ
SCSGCLK
Transmit Interrupt
Baud Rate Generator
Rx Enable
ShReceive
To
R
TSx
RRegister
From
CTSx
RTS_SEL
CTS_SEL
Data Bus
___
___
相關PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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