參數(shù)資料
型號: 7640
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述: 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù): 11/97頁
文件大?。?/td> 1885K
代理商: 7640
10
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.12.1 Single Chip
In this mode, all ports take on their primary function and
all internal memory is accessible. Those areas that are
not in internal memory are not accessible. Also, slow
memory wait and EDMA are disabled in this mode.
1.12.2 Memory Expansion
In this mode, Ports 0 and 1 output the address bus
(AB0-AB15), port 2 acts as the data bus input and out-
put, and port 3 bits 7 to 3 output RD, WR, SYNC
,
and DMA
, respectively. All memory areas that are not
internal memory or SFR area are accessed externally.
Because ports 0 to 3 lose their normal function in this
mode, the address area for the ports and their direction
registers are treated as external memory. In this mode,
slow memory wait and EDMA can be enabled.
1.12.3 Microprocessor
This mode is primarily the same as memory expansion
mode. The difference is that the internal ROM/EPROM
area can not be accessed and is instead treated as
external memory. Slow memory wait and EDMA can be
enabled in this mode.
1.12.4 Slow Memory Wait
The wait function is used when interfacing with external
memories that are too slow to operate at the normal
read/write speed of the MCU. When this is the case, a
wait can be used to extend the read/write cycle. Three
different wait modes are supported; software wait, RDY
wait, and extended RDY wait. The appropriate mode is
chosen by the setting of bits 0 to 3 of CPMB. The wait
function is disabled for internal memory and is valid only
for memory expansion and microprocessor modes.
,
Software wait is used to extend the read/write cycle by
one, two, or three cycles of . The cycle number is
determined by the value of bits 0 and 1 of CPMB. When
software wait is selected, the value on the RDY pin is
ignored. The timing for software wait is shown in Figure
1.9.
RDY wait is also used to extend the read/write cycle by
one, two, or three cycles . In this case, the read/write
cycle is extended if the RDY pin is low when
low (taking into account setup and hold times) at the
beginning of the read/write cycle. The extension time is
fixed by the value of bits 0 and 1 of CPMB and does not
depend on the state of the RDY pin once the read/write
cycle has begun. If the RDY pin is high when
low at the beginning of the read/write cycle, the read/
write cycle is not extended. The timing for RDY wait is
shown in Figure 1.10.
goes
goes
The extended RDY wait mode is used to extend the
read/write cycle by a variable number of cycles of
The exact number is dependent on the state of the RDY
pin and the value of bits 0 and 1 of CPMB. In this mode,
the read/write cycle is extended if the RDY pin is low
when
cycle. The read/write cycle continues to be extended
until the RDY pin is high when
point the read/write cycle completes in one, two, or three
cycles of
(with respect to the previous low to high
transition of ), dependent on the value in bits 0 and 1
of CPMB. If the RDY pin is high when
the beginning of the read/write cycle, the read/write cycle
is not extended. The timing for this mode is shown in
Figure 1.11.
goes low at the beginning of the read/write
goes low, at which
goes low at
The wait function can only be enabled for external
memory access in microprocessor or memory expan-
sion modes. However, the wait function can not be en-
abled for accesses to addresses 0008
to 000F
(Port
0 through Port 3 registers) in these modes, even though
the locations are mapped as external memory.
相關PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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