參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 64/97頁(yè)
文件大?。?/td> 1885K
代理商： 7640
63
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The
USB Endpoint x IN MAXP
, shown in Figure 1.66,
indicates the maximum packet size (MAXP) of an
Endpoint x IN packet. The default value for Endpoint 0
and 2-4 is 8. The default value for Endpoint 1 is 1. The
CPU can change this value as negotiated with the
host controller through the SET_DESCRIPTOR com-
mand. The setting of this register also affects the
configuration of single/dual packet operation. When
MAXP > 1/2 of the FIFO size, single packet mode is
set. When MAXP <= 1/ 2 of the FIFO size, dual
packet mode is set.
The
USB Endpoint x OUT MAXP
, shown in Figure
1.67, indicates the maximum packet size (MAXP) of
an Endpoint x OUT packet. The default value for End-
point 0 and 2-4 is 8. The default value for endpoint 1
is 1. For endpoint 0, the IN_MAXP and OUT_MAXP
registers shadow each other. Changing one register’s
value effectively changes the other register’s value.
The CPU can change this value as negotiated with the
host controller through the SET_DESCRIPTOR com-
mand. The setting of this register also affects the
configuration of single/dual packet operation. When
MAXP > 1/2 of the FIFO size, single packet mode is
set. When MAXP <= 1/2 of the FIFO size, dual packet
mode is set.
The
USB Endpoint x OUT WRT CNT Low
and the
USB Endpoint x OUT WRT CNT High
registers,
shown in Figure 1.68 and Figure 1.69, contain the
number of bytes in the Endpoint x OUT FIFO. The
USB FCU sets the values in these two Write Count
Registers after having successfully received a packet
of data from the host. The CPU reads these two reg-
isters to determine the number of bytes to be read
from the FIFO. The CPU should read WRT CNT Low
first and then WRT CNT High.
Fig. 1.68. USB Endpoint x OUT WRT CNT Low Register (WRT_CNTL)
Fig. 1.69. USB Endpoint x OUT WRT CNT High Register (WRT_CNTH)
Fig. 1.66. USB Endpoint x IN MAXP Register (IN_MAXP)
Fig. 1.67. USB Endpoint x OUT MAXP Register (OUT_MAXP)
Address: 005D
16
Access: R
Reset: 00
16
W_CNT7:0
Byte Count. This register contains the lower 8 bits of the byte count register
W_CNT7
W_CNT5
W_CNT4
W_CNT3
W_CNT2
W_CNT1
W_CNT0
MSB
7
LSB
0
W_CNT6
OMAXP7
OMAXP5
OMAXP4
OMAXP3
OMAXP2
OMAXP1
OMAXP0
MSB
7
LSB
0
OMAXP6
Address: 005C
16
Access: R/W
OMAXP7:0 Maximum packet size (MAXP) of Endpoint x OUT packet
MAXP = n for endpoint 0,2,3,4
MAXP = n * 8 for endpoint 1
n is the value written to this register. For endpoints that support a smaller
FIFO size, unused bits are not implemented(always write "0" to those bits)
IMAXP7
IMAXP5
IMAXP4
IMAXP3
IMAXP2
IMAXP1
IMAXP0
MSB
LSB
IMAXP6
Address: 005B
16
IMAXP7:0
Maximum packet size (MAXP) of Endpoint x IN packet
MAXP = n for endpoint 0,2,3,4
MAXP = n * 8 for endpoint 1
n is the value written to this register. For endpoints that support a smaller
W_CNT9:8
Byte Count. This register contains the upper 2 bits of the byte count register
Bits 7:2
Reserved (Read "0")
Address: 005E
16
Access: R
Reset: 00
16
Reserved
Reserved
Reserved
Reserved
Reserved
W_CNT9
W_CNT8
MSB
7
LSB
0
Reserved
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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