參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 46/97頁
文件大?。?/td> 1885K
代理商： 7640
45
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19.4.2 Receive Method
Set up
Define the baud rate by writing a value from 0-255 into
UxBRG.
Set the Receive Initialization Bit (RIN, bit 3 in the
UxCON), to "1".
Configure the data format and the clock selection by
writing the appropriate value to UxMOD.
Set the Request-To-Send Enable Bit (RTS_SEL, bit 6
of UxCON), if RTS handshaking will be used.
Set the Receive Enable Bit (REN, bit 1 in the
UxCON), to "1".
Operation
When a falling edge is detected on the URXDx pin,
the value on the pin is sampled at the basic clock rate,
which is 16 times faster than the baud rate. If the pin is
low for at least two cycles of the basic clock, the start
bit is detected. Sampling is again performed three
times in the approximate middle of the start bit. If two
or more of the samples are low, the start bit is deemed
valid. If two or more of the samples are not low, the
start bit is invalidated and the UART again begins wait-
ing for a falling edge on the URXDx pin.
Fig. 1.45. UART Transmit Operation Waveform
UxTRB1
Write
UxBRG
Clock
UTXDx
TBE
Start bit
D0
Stop bit
Start bit
Stop bit
TCM
Once a valid start bit has been detected, input data re-
ceived through the URXDx pin is read one bit at a time,
LSB first, into the receive shift register. As is the case
with the start bit, three samples are taken in the ap-
proximate middle of each data bit, the parity bit, and
the stop bit(s). If two or more of the samples are low, a
"0" is latched, and if two or more of the samples are
high, a "0" is latched.
When the number of bits specified by the data format
has been received and the last stop bit is detected, the
contents of the receive shift register are transferred to
the receive buffer and the Receive Buffer Full Flag in
the UxSTS is set to a "1", if a receive error has not oc-
curred (see Figure 1.46). The RBF interrupt request is
also generated at this time if a receive error has not oc-
curred. However, if a receive error did occur, the
appropriate error flags are set and the Receive Error
Sum (SER) interrupt request is generated at this time.
When the low-order byte of the receive buffer
(UxTRB1) is read, the Receive Buffer Full Flag is
cleared, and the receive buffer is now ready for the next
byte. If 9-bit character length has been selected, the
high-order byte of the receive buffer (UxTRB2) should
be read before reading the low-order byte (UxTRB1).
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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