參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 27/97頁
文件大?。?/td> 1885K
代理商： 7640
26
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.15 INTERRUPT CONTROL UNIT
This section details a specialized peripheral, the inter-
rupt control unit (ICU).
This series supports a maximum of 23 maskable inter-
rupts, one software interrupts, and one reset vector
that is treated as a non-maskable interrupt.
Table 1.6 describes the interrupt registers. See Table
1.7 for the interrupt sources, jump destination ad-
dresses, interrupt priorities, and section references
for the interrupt request sources.
Table 1.7. Interrupt Vector
Table 1.6. Interrupt Registers
Address
Description
Acronym and
Value at Reset
IREQA=00
IREQB=00
IREQC=00
ICONA=00
ICONB=00
ICONC=00
IPOL=00
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0011
16
Interrupt request register A
Interrupt request register B
Interrupt request register C
Interrupt control register A
Interrupt control register B
Interrupt control register C
Interrupt polarity selection
register
Jump Destination
Storage Address
(Vector Address)
High-order
Byte
FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFF1
FFEF
FFED
FFEB
FFE9
FFE7
FFE5
FFE3
FFE1
FFDF
FFDD
FFDB
FFD9
FFD7
FFD5
FFD3
FFD1
FFCF
FFCD
FFCB
Remarks
Priority
Interrupt
Low-order
Byte
FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFEE
FFEC
FFEA
FFE8
FFE6
FFE4
FFE2
FFE0
FFDE
FFDC
FFDA
FFD8
FFD6
FFD4
FFD2
FFD0
FFCE
FFCC
FFCA
Reference
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
RSRV1
RSRV2
RESET
USB
SOF
INT0
INT1
DMA1
DMA2
U1RBF
U1TX
U1ES
U2RBF
U2TX
U2ES
TX
TY
T1
T2
T3
CNTR0
CNTR1
SIO
IBF
OBE
KEY
BRK
Reserved for factory use
Reserved for factory use
User RESET (Non-Maskable)
USB Function Interrupt
USB SOF Interrupt
External Interrupt 0
External Interrupt 1
DMAC Channel 0 Interrupt
DMAC Channel 1 Interrupt
UART1 Receiver Buffer Full
UART1 Transmit Interrupt
UART1 Error Sum Interrupt
UART2 Receiver Buffer Full
UART2 Transmit Interrupt
UART2 Error Sum Interrupt
Timer X Interrupt
Timer Y Interrupt
Timer 1 Interrupt
Timer 2 Interrupt
Timer 3 Interrupt
External CNTR0 Interrupt
External CNTR1 Interrupt
SIO Interrupt
Input Buffer Full Interrupt
Output Buffer Empty Interrupt
Key-on Wake Up
BRK Instruction (Non-Maskable)
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
LSB
Section 1.21.2.1
Section 1.21.2.2
Section 1.15.1
Section 1.15.1
Section 1.23
Section 1.23
Section 1.19.4.2
Section 1.19.4.1
Section 1.19.4.2
Section 1.19.4.2
Section 1.19.4.1
Section 1.19.4.2
Section 1.17
Section 1.17
Section 1.17
Section 1.17
Section 1.17
Section 1.17.1.2
Section 1.17.2
Section 1.18
Section 1.22
Section 1.22
Section 1.16
MSB
LSB
I
MSB
LSB
I
MSB
I
C
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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