參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 74/97頁
文件大?。?/td> 1885K
代理商： 7640
73
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Note 1:
Stop mode stops the oscillators that are also the inputs to the frequency synthesizer. However, the
frequency synthesizer is not disabled and so its output is unstable. So, always set the system clock
to an external oscillator and disable the frequency synthesizer before entering stop mode.
Note 2:
= f(X
in
)/4 can be interchanged with
cases.
= f(X
in
)/2 by setting CCR7 to “1”. The same flow chart applies to both
Note 3:
The input to the frequency synthesizer is independent of the system clock. It can be either X
in
or XC
in
depend
ing on bit 3 of FSC. In the above flow, the input has been chosen to be the same as the system clock only for
simplicity. The oscillator selected to be the input to the frequency synthesizer must be enable before the
frequency synthesizer is enabled.
Note 4:
The input clock for the frequency synthesizer must be set to XC
in
by setting FIN (bit 3 of FSC) to a "1" before
X
in
oscillation can be disabled.
Note:
CPMA values shown assume single-chip mode with stack in one page.
Xin clock stopped
XCin clock on
PLL clock stopped
Φ
C=f(XCin)/2
Xin clock stopped
XCin clock on
PLL clock on
Note 3
Φ
=f(XCin)/2
CPMA7=BC, FSC=49
Xin clock stopped
XCin clock on
PLL clock on
Φ
=f(PLL)/2
CPMA7=FC, FSC=49
Xin clock on
XCin clock on
PLL clock on
Φ
=f(PLL)/2
CPMA=DC, FSC=41
Xin clock on
XCin clock on
PLL clock on
Note 3
Φ
=f(XCin)/2
CPMA=9C, FSC=41
Xin clock on
XCin clock on
PLL clock stopped
Φ
=f(XCin)/2
CPMA=9C, FSC=60
Xin clock on
XCin clock on
PLL clock stopped
Φ
=f(Xin)/4
Note 2
CPMA=1C, FSC=60
Xin clock on
XCin clock on
Note 3
Φ
=f(Xin)/4
Note 2
CPMA=1C, FSC=41
Xin clock on
XCin clock on
PLL clock on
Φ
=f(PLL)/2
CPMA=5C, FSC=41
Xin clock on
XCin clock stopped
PLL clock on
Φ
=f(PLL)/2
CPMA=4C, FSC=41
Stop
Note 1
Wait
Stop
Note 1
Wait
Stop
Note 1
Wait
Stop
Note 1
Wait
Wait
Wait
Wait
Wait
RESET
FSC0
1
CPMA6
1
1
0
CPMA4
CPMA7
CPMA5
Note 4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FSC0
FSC0
FSC0
CPMA6
CPMA6
CPMA6
Xin clock on
XCin clock stopped
PLL clock stopped
Φ
=f(Xin)/4
Note 2
CPMA=0C, FSC=60
Xin clock on
XCin clock stopped
PLL clock on
Note 3
Φ
Note 2
C=f(Xin)/4
Fig. 1.90. Clock Flow Diagram
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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