參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 62/97頁(yè)
文件大小： 1885K
代理商： 7640
61
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INXCSR3 (ISO/TOGGLE_INIT):
When the endpoint is
used for isochronous data transfer, the CPU sets this
bit to a “1” for the entire duration of the isochronous
transfer. With the ISO bit set to a “1”, the device uses
DATA0 as the PID for all packets sent back to the
host.
When the endpoint is required to initialize the data
toggle sequence bit (reset to DATA0 for the next data
packet), the CPU sets this bit to a “1” and then resets
it to a “0” to initialize the respective endpoint’s data
toggle.
As with any other method to initialize the data toggle,
this set/reset of the TOGGLE_INIT bit method as-
sumes that there is no active IN transaction to the
respective endpoint on the bus at the time the initial-
ization process is ongoing. Set/reset of the
TOGGLE_INIT bit is performed only when an end-
point experiences a configuration event.
INXCSR4 (INTPT):
The CPU writes a “1” to this bit to
initialize this endpoint as a status change endpoint for
IN transactions. This bit is set only if the correspond-
ing endpoint is to be used to communicate rate
feedback information (see section 1.21.3.1 for de-
tails).
INXCSR5 (TX_FIFO_NOT_EMPTY):
The USB FCU
sets this bit to a “1” when there is data in the IN FIFO.
This bit in conjunction with IN_PKT_RDY bit will pro-
vide the transmit FIFO status information (see section
1.21.3.1 for details).
INXCSR6 (FLUSH):
The CPU writes a “1” to this bit
to flush the IN FIFO. If there is one packet in the IN
FIFO, a flush will cause the IN FIFO to be empty. If
there are two packets in the IN FIFO, a flush will
cause the older packet to be flushed out from the IN
FIFO. Setting the INXCSR6 (FLUSH) bit during trans-
mission could produce unpredictable results.
INXCSR7 (AUTO_SET):
If the CPU sets this bit to a
“1”, the IN_PKT_RDY bit is set automatically by the
USB FCU after the number of bytes of data equal to
the maximum packet size (MAXP) are written into the
IN FIFO (see section 1.21.3.1 for details).
All bits in
USB Endpoint 0 OUT CSR (Control &
Status Register)
, shown in Figure 1.64, are reserved
(all control and status information is in Endpoint 0 IN
CSR)
Fig. 1.64. USB Endpoint 0 OUT CSR (OUT_CSR)
Bits 7:0
Reserved (Read "0")
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
MSB
7
LSB
0
Reserved
Address: 005A
16
Access: R
Reset: 00
16
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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