參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 29/97頁
文件大小： 1885K
代理商： 7640
28
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 1.30. Interrupt Polarity Register (IPOL)
Fig. 1.29. Interrupt Control Register C (ICONC)
Fig. 1.28. Interrupt Control Register B (ICONB)
Fig. 1.27 Interrupt Control Register A (ICONA)
ICA5
ICA4
ICA2
ICA1
ICA0
MSB
LSB
0
ICA3
ICA7
ICA6
ICA 0
ICA 1
ICA 2
ICA 3
ICA 4
ICA 5
ICA 6
ICA 7
USB Function Interrupt Enable (bit 0)
USB SOF Interrupt Enable (bit 1)
External Interrupt 0 Enable (bit 2)
External Interrupt 1 Enable (bit 3)
DMAC channel 0 Interrupt Enable (bit 4)
DMAC channel 1 Interrupt Enable (bit 5)
UART1 Receive Buffer Full Interrupt Enable (bit 6)
UART1 Transmit Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Address: 0005
16
Access: R/W
Reset: 00
16
The interrupt polarity register allows the user to se-
lect the edge that will trigger an external interrupt
Reserved
Reserved
Reserved
INT1 Pol INT0 Pol
MSB
7
LSB
0
Reserved
Reserved
Reserved
Address: 0011
16
Access: R/W
Reset: 00
16
INT0 Pol
INT0 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
INT1 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
Reserved (Read/Write “0”)
INT1 Pol
Bits 2-7
request. The polarity register (IPOL) for the external
interrupts is shown in Figure 1.30.
ICC 0
ICC 1
ICC 2
ICC 3
ICC 4
ICC 5
ICC 6
Timer 3 Interrupt Enable (bit 0)
External CNTR0 Interrupt Enable (bit 1)
External CNTR1 Interrupt Enable (bit 2)
SIO Interrupt Enable (bit 3)
Input Buffer Full Interrupt Enable (bit 4)
Output Buffer Empty Interrupt Enable (bit 5)
Key-on Wake up Interrupt Enable (bit 6)
0: Interrupt Disable
1: Interrupt Enable
ICC 7
Reserved (Read/Write “0”)
Address: 0007
16
Access: R/W
Reset: 00
16
ICC5
ICC4
ICC2
ICC1
ICC0
MSB
7
LSB
0
ICC3
ICC6
Reserved
ICB5
ICB4
ICB2
ICB1
ICB0
MSB
7
LSB
0
ICB3
ICB7
ICB6
ICB 0
ICB 1
ICB 2
ICB 3
ICB 4
ICB 5
ICB 6
ICB 7
UART1 Error Sum Interrupt Enable (bit 0)
UART2 Receive Buffer Full Interrupt Enable (bit 1)
UART2 Transmit Interrupt Enable (bit 2)
UART2 Error Sum Interrupt Enable (bit 3)
Timer X Interrupt Enable (bit 4)
Timer Y Interrupt Enable (bit 5)
Timer 1 Interrupt Enable ( bit 6)
Timer 2 Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Address: 0006
16
Access: R/W
Reset: 00
16
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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