參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 40/97頁(yè)
文件大?。?/td> 1885K
代理商： 7640
39
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.2 SIO Normal Operation
An internal clock or an external clock can be selected
as the synchronous clock. When the internal clock is
chosen, dividers are built in to provide eight different
clock selections. The start of a transfer is initiated by
a write signal to the SIO shift register (address
002A
16
). The SRDY signal then drops active low. On
the negative edge of the transfer clock SRDY returns
high and the data is transmitted out the STXD pin.
Data is latched in from the SRXD pin on the rising
edge of the transfer clock. If an internal clock is se-
lected, the STXD pin enters a high-impedance state
after an 8-bit transfer is completed. If an external
clock is selected, the contents of the serial I/O regis-
ter continue to be shifted while the send/receive clock
is being input. Therefore, the clock needs to be con-
trolled by the external source. Also there is no STXD
high-impedance function after data is transferred.
Regardless of whether an internal or external clock is
selected, after an 8-bit transfer, the interrupt request
bit is set. Figure 1.39 shows the timing for the serial I/
O with the LSB-first option selected.
Synchronous Clock
Transfer Clock
SIO Register
Write Signal
Receive Enable
Signal SRDY
SIO Output
SIO Input
Interrupt Request Bit Set
See Note
Note:
When the internal clock is selected, the TxD pin goes into high-
impedance after the data is transferred.
D0 D1 D2 D3
D4 D5 D6 D7
Fig. 1.39. Normal Mode SIO Function Timing (with LSB-First selected)
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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