參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 36/97頁
文件大?。?/td> 1885K
代理商： 7640
35
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.17.3 Timer 1
Timer 1 is an 8-bit timer with an 8-bit reload latch and
has a pulse output option (see Figure 1.35).
T123M7 of Timer123 mode register (T123M) is the
Timer 1 and 2 Data Write Control Bit. If T123M7 is “1”,
data written to Timer 1 is placed only in the Timer 1
reload latch. The latch value is loaded into Timer 1 af-
ter Timer 1 underflows. If T123M7 is “0”, the value
written to Timer 1 is placed in Timer 1 and the Timer
1 reload latch. At reset, T123M7 is set to a “0”.
The output signal TOUT is controlled by T123M5 and
T123M6. T123M5 controls the polarity of TOUT. Set-
ting the bit T123M5 to “1” causes TOUT to start at a
low level, and clearing this bit to “0” causes TOUT to
start at a high level. Setting T123M6 to “1” enables
TOUT, and clearing T123M6 to “0” disables TOUT.
Timer Mode
Count Source: /8 or XCin/2
In Timer mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into
the timer, and the count down sequence begins
again.
Pulse Output Mode
Count Source: /8 or XCin/2
Timer 1 Pulse Output mode is enabled by setting
T123M6 to “1” and T123M0 to a “0”. Each time the
Timer 1 underflows, the output of the TOUT pin is
inverted, and the corresponding Timer 1 interrupt
request bit is set to a “1”. The repeated inversion of
the TOUT pin output produces a rectangular wave-
form with a duty ratio of 50 percent. The initial level
of the output is determined by the TOUT polarity se-
lect bit (T123M5). When this bit is “0”, the output
starts from a high level. When this bit is “1”, the out-
put starts from a low level.
Fig. 1.35. Timer 1, 2, 3 Mode Register (T123M)
T123M0
TOUT Source Selection Bit (bit 0)
0: TOUT = Timer 1 output
1: TOUT = Timer 2 output
Timer 1 Stop Bit (bit 1)
0: Timer running
1: Timer stopped
Timer 1 Count Source Select Bit (bit 2)
0:
divided by 8
1: XCin divided by 2
Timer 2 Count Source Select Bit (bit 3)
0: Timer 1 underflow signal
1:
Timer 3 Count Source Select Bit (bit 5)
0: Timer 1 underflow signal
1:
divided by 8
TOUT Output Active Edge Selection Bit (bit 5)
0: Start on high output
1: Start on low output
TOUT Output Control Bit (bit 6)
0: TOUT output disabled
1: TOUT output enabled
Timer 1 and 2 Data Write Control Bit (bit 7)
0: Write data in latch and timer
1: Write data in latch only
T123M1
T123M2
T123M3
T123M4
T123M5
T123M6
T123M7
T123M7
T123M5
T123M4
T123M3
T123M2
T123M1
T123M0
MSB
7
LSB
0
Address: 0029
16
Access: R/W
Reset: 00
16
T123M6
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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