參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 41/97頁(yè)
文件大?。?/td> 1885K
代理商： 7640
40
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.3 SPI Compatible Operation
Setting the SPI bit (bit 0 in SIOCON2) puts the SIO in
an SPI compatible mode. The internal/external clock
select bit (bit 6 in SIOCON1) determines whether the
SIO is an SPI master or slave. If internal clock is se-
lected the SIO is a master, and if external clock is
selected the SIO is in slave mode.
Entering SPI mode has the following effects on opera-
tion:
1. The RxD pin functions as a MISO (Master In/Slave
Out) pin. This means that when the SPI is in slave
mode transmit data will be output on this pin. In mas
ter mode receive data is input on this pin.
2. The TxD pin functions as a MOSI (Master Out/Slave
In) pin. When the SPI is in slave mode receive data is
input on this pin. In master mode this pin drives the
transmit data.
3. The SRDY pin functions as a slave/chip select. If the
SPI is in slave mode, this pin functions as a slave se
lect input. When configured as an SPI master, the
SRDY pin functions as a chip select output.
Figure 1.40 shows the four possible SPI clock-to-data
relationships.
The CPol and CPha bits (bits 3 and 4 in SIOCON2)
are used to select the format.
1.18.3.1 SPI Slave Mode
When configured as an SPI slave the SIO does not
initiate any serial transfers. All transfers are initiated
by an external SPI bus master. When the CPha (bit 4
in SIOCON2) is “0” serial transfers begin with the fall-
ing edge of the SRDY input. For CPha = “1” serial
transfers begin when the SCLK leaves its idle state
(the clock idle state is defined by CPol, bit 3 in
SIOCON2).
If SRDY is held high, the shift clock is inhibited, SRXD
(MISO) is tri-stated, and the shift count is reset. If
SRDY is held low, then the shift operation is per-
formed. The SRDY input must be deasserted
(brought high) between transfers; this resets the
SIO’s internal bit counter.
When the SIO is in SPI slave mode, all transfers are
initiated by an external SPI bus master, not by the
MCU. Therefore, an application must implement
some form of handshaking or synchronization to
avoid writing to the SIO shift register during a serial
transfer. Writing to the SIO shift register during a
transfer will corrupt the transfer in progress.
SCLK
First bit
Last bit
SCLK
SCLK
SCLK
SRDY
TxD/RxD
Arrows indicate edge when data is captured
CPol = 1
CPha = 1
CPol = 0
CPha = 1
CPol = 1
CPha = 0
CPol = 0
CPha 0
Fig. 1.40. SPI Compatible Transmission Formats
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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