參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 23/97頁
文件大?。?/td> 1885K
代理商： 7640
22
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.6 Port P7
Port P7 is a 5-bit general purpose I/O port that can be
configured to access special second functions.
Port P7
0
This pin is multiplexed with the USB start of frame
pulse (SOF) output. When USBC6 is a “1”, this pin
outputs the USB SOF.
Port P7
1
This pin is multiplexed with the HOLD function. When
the MCU is in memory expansion or microprocessor
mode and CPMB5 is set to “1”.
Port P7
2
This pin is multiplexed with the S
1
input control signal
from a Master CPU. When DBBC17 is “1”, the pin
takes on the function of the S
1
input control signal.
Port P7
3
This pin is multiplexed with the IBF
1
output control
signal for a Master CPU and the HLDA function.
When DBBC11 and DBBC17 are “1”, the pin takes on
the function of the IBF
1
output control signal. When
the MCU is in memory expansion or microprocessor
mode, CPMB5 is set to “1”, and the IBF
1
function is
not enabled.
Port P7
4
This pin is multiplexed with the OBF
1
control pin for
the bus interface control block. P7
4
acts as OBF
1
out-
put to a Master CPU when DBBC10 and DBBC17 are
“1”.
Fig. 1.19. Port P7 Block Diagram
Direction Register
Data Bus
Port Latch
USBC6
SOF
Data Bus
Port Latch
Direction Register
CPMB5
CPMB5
HOLD
Data Bus
Port Latch
Direction Register
DBBC17
DBBC17
S
1
Direction Register
Data Bus
Port Latch
IBF
1
HLDA
DBBC17
DBBC11
CPMB5
Direction Register
Data Bus
Port Latch
DBBC10
DBBC17
OBF
1
Port P7
0
Port P7
1
Port P7
2
Port P7
3
Port P7
4
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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