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參數(shù)資料
| 型號： | XRT82L34 |
| 廠商： | Exar Corporation |
| 英文描述： | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| 中文描述： | 四路T1/E1/J1收發(fā)線收發(fā)器時鐘恢復和抖動衰減器（四的T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）） |
| 文件頁數(shù)： | 6/50頁 |
| 文件大?。?/td> | 648K |
| 代理商： | XRT82L34 |
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XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
á
PRELIMINARY
4
PIN DESCRIPTION
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
1
RxCLK0
O
Receiver 0 Clock Output
2
RxLOS0
O
Receiver 0 Loss of Signal
. This signal is asserted "High" to indicate loss of
signal at the receive input.
3
TxNEG0
I
Transmitter 0 Negative NRZ Data Input
. In dual-rail mode, this signal is the n-
rail input data for transmitter 0. In single-rail mode, this pin can be left uncon-
nected.
N
OTE
:
Internally pulled -up with a 50k
resistor.
4
TxPOS0/
TData0
I
Transmitter 0 Positive Data Input
. In dual-rail mode, this signal is the p-rail
input data for transmitter 0.
Transmitter 0 Data Input
. In single-rail mode, this pin is used as the NRZ input
data for transmitter 0.
N
OTE
:
Internally pulled -up with a 50k
resistor.
5
TxClk0
I
Transmitter 0 Clock Input
.
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm. During normal
operation both in Host Mode and Hardware Mode, TxClk is used for sampling
input data at TxPOS/TData and TxNEG, while MCLK is used as the timing refer-
ence for the transmit pulse shaping circuit. In Hardware Mode, if TxClk is tied
"High" for more than 10 μs, then TAOS (a continuous all one's AMI signal) will be
transmitted to the line using MCLK as timing reference.
If TxClk0 is tied “Low” for more than 10 μs, the transmitter will be powered down
and the output will be tri-stated.
N
OTES
:
1. Internally pulled -up with a 50k
resistor.
2. SeeFigure 10 and Figure 11.
6
RESET
I
Hardware Reset
(Active Low). When this pin is tied Low for more than 10mS,
the device is put in the reset state.
N
OTE
:
Internally pulled -up with a 50k
resistor.
7
PTS1
CLKE
I
I
Processor Type Select bit 1:
Host Mode
In Host Mode the appropriate bits are set in the command mode
Hardware Mode
Clock Edge:
In Hardware Mode, connect this pin Low to select falling edge of TxClk to sam-
ple input data and also select RxPOS/RxNEG data to be valid on falling edge of
RxClk. Connect this pin "High" to select rising edge of TxClk to sample input
data and also selects RxPOS/RxNEG data to be updated on the rising edge of
RxClk.
8HC11,8081,80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Intel i906,Motorola 860 (sync.)
PTS1
0
1
0
1
PTS2
0
0
1
1
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