參數(shù)資料
型號: XRT82L34
廠商: Exar Corporation
英文描述: Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器(帶時鐘恢復(fù)和振蕩衰減器))
中文描述: 四路T1/E1/J1收發(fā)線收發(fā)器時鐘恢復(fù)和抖動衰減器(四的T1/E1/J1線收發(fā)器(帶時鐘恢復(fù)和振蕩衰減器))
文件頁數(shù): 40/50頁
文件大?。?/td> 648K
代理商: XRT82L34
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
á
PRELIMINARY
38
Motorola Interface Timing
The signals used in the Motorola microprocessor in-
terface mode are: Address Strobe (AS), Data Strobe
(DS), Read/Write Enable (R/W), Chip Select (CS),
Address and Data bits. The interface is compatible
with the timing of a Motorola 68000 microprocessor
family with up to 16.67 MHz clock frequency. The in-
terface timing is shown in Figure 21, Figure 22 and
Figure 23. The I/O specifications are shown in
Table 20.
T
ABLE
19: I
NTEL
I
NTERFACE
T
IMING
S
PECIFICATIONS
SYMBOL
P
ARAMETER
M
IN
T
YP
M
AX
C
ONDITION
t
64
A8 - A0 Setup Time to ALE_AS
Low
4
ns
t
65
A8 - A0 Hold Time from ALE_AS
Low.
2
ns
Intel Type Read Operation
t
66
RDS_DS Pulse Width
260
ns
t
67
Data Valid from RDS_DS* Low.
240
ns
t
68
Data Bus Floating from
RDS_DS* High
2
ns
t
69
ALE to RD Time
4
ns
t
701
RD Time to "NOT READY" (e.g.,
RDY_DTCK toggling "Low")
145
ns
t
76
Minimum Time between Read
Burst Access (e.g., the rising
edge of RD to falling edge of RD)
60
ns
Intel Type Write Operations
t
71
Data Setup Time to WR_R/W
High
160
ns
t
72
Data Hold Time from WR_R/W
High
0
ns
t
73
High Time between Reads and/
or Writes
60
ns
t
74
ALE to WR Time
4
ns
t
77
Min Time between Write Burst
Access (e.g., the rising edge of
WR to the falling edge of WR)
60
ns
t
770
CS Assertion to falling edge of
WR_R/W
20
ns
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