參數(shù)資料
型號(hào)： XRT82L34
廠商： Exar Corporation
英文描述： Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）)
中文描述： 四路T1/E1/J1收發(fā)線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器（四的T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器））
文件頁(yè)數(shù)： 15/50頁(yè)
文件大?。?/td> 648K
代理商： XRT82L34
á
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
13
SYSTEM-FUNCTIONAL DESCRIPTION
A simplified single channel block diagram of the
XRT82L34 is presented in Figure 1. The XRT82L34
consists of four identical transmit and receive chan-
nels for E1(2.048 Mbps) and T1(1.544 Mbps) PCM
systems. The operational mode of each channel of
the line interface can be configured by the micropro-
cessor interface (Host Mode) or by Hardware control.
RECEIVER
At the receiver input, cable attenuated AMI signals
can be coupled to the receiver using a capacitor or a
2:1 step-down transformer. The receive signal first
goes through the equalizer for signal conditioning be-
fore being applied to the data recovery circuit. The
data recovery circuit includes a peak detector which
is set typically at 50% for E1 (65% for T1) of the
equalizer output peak amplitude for data slicing. After
the data slicers, the digital representation of the AMI
signals goes to the clock recovery circuit for timing re-
covery and subsequently to the HDB3 or B8ZS de-
coder (if selected) before they are output via the Rx-
POS/RDATA and RxNEG/LCV pins. The digital data
output can be in dual-rail or single-rail mode depend-
ing on the option selected. Clock and timing recovery
is accomplished by means of a digital PLL scheme
which can tolerate high input jitter and meets or ex-
ceeds the jitter tolerance requirements as specified in
the ITU - G.823 and Bellcore GR-499-CORE stan-
dards.
JITTER ATTENUATOR
To reduce jitter in the transmit line signal or recovered
clock and data signals, a crystal-less jitter attenuator
with a 32x2 bit or 64x2 bit FIFO is provided for each
channel. The jitter attenuator can be configured to op-
erate in either the transmit or receive path, or it can
be disabled through Host or Hardware Mode control.
The jitter attenuator design is based on a digital
scheme that uses the MCLK signal as a reference in-
put. No other high frequency clock is necessary. With
the jitter attenuator selected, the typical throughput
delay is 16 bits for a 32 bit FIFO depth or 32 bit for a
64 bit FIFO depth. The design of the jitter attenuator
is such that if the write and read pointers of the FIFO
are within two bits of overflowing or underflowing, the
bandwidth of the jitter attenuator is automatically wid-
ened in order to permit the “Jitter Attenuator” PLL to
track the short term input jitter to avoid data corrup-
tion. When this situation occurs, the jitter attenuator
will not attenuate input jitter until the read/write point-
er's position is outside the two bit window. Under nor-
mal condition, the jitter transfer characteristic meets
the narrow bandwidth requirement as specified in
ITU- G.736, ITU- I.431 and AT&T Pub 62411 stan-
dards.
HDB3/B8ZS DECODER
The decoder function is only active if the chip has
been configured to operate in the single-rail mode.
When the single-rail mode is selected, the receive
line signal will be decoded according to HDB3 rules
for E1 and B8ZS for T1. Further, any bipolar
violaHDB3 or B8ZS line coding scheme will be
flagged as a Line Code Violation via the LCV output
pin. The LCV output pin will be pulsed high for one
RxClk cycle for each line code violation that is detect-
ed. Excessive number of zeros in the receive data
stream are also flagged as a line code violation via
the same output pin. If AMI decoding is selected in
single-rail mode operation, every bipolar violation in
the receive data stream is reported as error at the
LCV pin.
RECEIVER LOSS OF SIGNAL (LOS)
The receiver loss of signal monitoring function is im-
plemented using both analog and digital detection
schemes compatible with ITU G.775 requirements.
When the amplitude of the E1 or T1 line signal at
RTIP/RRING drops 20dB below the 0dB nominal lev-
el, the digital circuit is activated to parse through and
check for 32 consecutive zeros in E1 and 175 zeros in
T1 modes, before LOS is asserted to indicate loss of
input signal. The number of consecutive zeros before
LOS is declared can be increased to 4096 bits in both
E1 and T1 mode (when operating in the Host Mode).
The LOS condition is cleared when the input signal
rises above 20dB below 0dB nominal level and meets
12.5% density of 4 ones in a 32 bit window with no
more than 16 consecutive zeros for E1 and 16 ones
in a 128 bit window with no more than 100 consecu-
tive zeros in the T1 data stream.
CLOCK SIGNALS GENERATED WHEN LOS IS
DECLARED
The output signal at the RxClk output pin depends
upon the type of LOS condition that is occurring.
Complete Loss of Signal (Zero Amplitude)
If the XRT82L34 experiences a complete Loss of Sig-
nal (e.g., no signal amplitude), then the XRT82L34
Clock Recovery PLL enters the Training Mode, an Dif-
ferentially begins to lock onto the signal applied to the
MCLK input pin. As a consequence, the Clock Recov-
ery PLL will begin to drive a clock signal to the Termi-
nal Equipment (via the RxClk output pin), which is de-
rived from the MCLK input pin.
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