- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376463 > XRT82L34 (Exar Corporation) Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) PDF資料下載
參數(shù)資料
| 型號： | XRT82L34 |
| 廠商： | Exar Corporation |
| 英文描述： | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| 中文描述： | 四路T1/E1/J1收發(fā)線收發(fā)器時鐘恢復和抖動衰減器（四的T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）） |
| 文件頁數(shù)： | 11/50頁 |
| 文件大?。?/td> | 648K |
| 代理商： | XRT82L34 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
á
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
9
58
D[5]
LOOPSEL
I/O
I
Data Bus[5]
.
Microprocessor read/write data bus.
Loop-back Mode Select
.
In Hardware Mode, if LOOPEN(0-3) is “High”, this pin is used for selecting loop-
back mode. Connect this pin "High" to select local loop-back and Low to select
remote loop-back. Digital Loop-back is not supported in Hardware Mode.
N
OTE
:
Internally pulled -up with a 50k
resistor.
59
D[4]
LOOPEN3
I/O
I
Data Bus[4]
.
Microprocessor read/write data bus.
Loop-back Enable
.
In Hardware Mode, connect this pin “High” to enable channel 3 loop-back oper-
ation. Remote or local loop-back is determined by pin 58 setting. Digital Loop-
back is not supported in Hardware Mode.
N
OTE
:
Internally pulled -up with a 50k
resistor.
60
D[3]
LOOPEN2
I/O
I
Data Bus[3]
.
Microprocessor read/write data bus.
Loop-back Enable
.
In Hardware Mode, connect this pin "High" to enable channel 2 loop-back oper-
ation. Remote or local loop-back is determined by pin 58 setting. Digital Loop-
back is not supported in Hardware Mode.
N
OTE
:
Internally pulled -up with a 50k
resistor.
61
D[2]
LOOPEN1
I/O
I
Data Bus[2]
.
Microprocessor read/write data bus.
Loop-back Enable
.
In Hardware Mode, connect this pin "High" to enable channel 1 loop-back oper-
ation. Remote or local loop-back is determined by pin 58 setting. Digital Loop-
back is not supported in Hardware Mode.
N
OTE
:
Internally pulled -up with a 50k
resistor.
62
D[1]
LOOPEN0
I/O
I
Data Bus[1]
.
Microprocessor read/write data bus.
L
oop-back Enable
.
In Hardware Mode, connect this pin “High” to enable channel 0 loop-back oper-
ation. Remote or local loop-back is determined by pin 58 setting. Digital Loop-
back is not supported in Hardware Mode.
N
OTE
:
Internally pulled -up with a 50k
resistor.
63
D[0]
FIFOS
I/O
I
Data Bus[0]
.
Microprocessor read/write data bus.
FIFO Size Select.
In Hardware Mode, connect this pin "High" selects 64 bit FIFO depth and con-
nect Low to select 32 bit FIFO depth.
N
OTE
:
Internally pulled -up with a 50k
resistor.
64
DVDD
****
Digital Positive Supply(3.3V± 5%)
65
DGND
****
Digital Ground
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83L314 | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
| XRT83L314IB | 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。