參數(shù)資料
型號： XRT82L34
廠商： Exar Corporation
英文描述： Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）)
中文描述： 四路T1/E1/J1收發(fā)線收發(fā)器時鐘恢復(fù)和抖動衰減器（四的T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器））
文件頁數(shù)： 10/50頁
文件大?。?/td> 648K
代理商： XRT82L34
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
á
PRELIMINARY
8
48
DVDD(PLL)
****
Analog Positive Supply(3.3V± 5%), used for PLL
49
RxNEG2/LCV2
O
Receiver 2 Negative Data Output:
In dual-rail mode, n-rail data are sent to the framer.
Line Code Violation Output:
In single-rail mode, this signal output "High" for one receive clock cycle to indi-
cate a code violation is detected in the received data. If AMI coding is selected,
every bipolar violation received will cause this pin to go "High".
50
RxPOS2/
RData2
O
Receiver 2 Positive Data Output:
In dual-rail mode, p-rail data are sent to the framer.
Receiver 2 NRZ Data Output:
In single-rail mode, the received data are sent in NRZ format to the framer.
51
RxClk2
O
Receiver 2 Clock Output.
52
RxLOS2
O
Receiver 2 Loss of Signal
. This signal is asserted "High" to indicate loss of
signal at the receive input.
53
TxNEG2
I
Transmitter 2 Negative Data Input
. In dual-rail mode, this signal is the n-rail
data input for transmitter 2.
In single-rail mode, this pin can be left unconnected.
N
OTE
:
Internally pulled -up with a 50k
resistor.
54
TxPOS2/
TData2
I
Transmitter 2 Positive Data Input
.
In dual-rail mode, this signal is the p-rail input data for transmitter 2.
Transmitter 2 NRZ Data Input
.
In single-rail mode, this pin is used as the NRZ input data for transmitter 2.
N
OTE
:
Internally pulled -up with a 50k
resistor.
55
TxClk2
I
Transmitter 2 Clock Input
.
E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ±32ppm(see pin 5 descrip-
tion for other usage of this pin.)
N
OTE
:
Internally pulled -up with a 50k
resistor.
56
D[7]
TXJA
I/O
I
Data Bus[7]
.
Microprocessor read/write data bus.
Transmit Jitter Attenuator Select
.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the trans-
mit path and connect Low to disable jitter attenuator.
Setting RXJA simultaneously "High" also disables jitter attenuator selection.
N
OTE
:
Internally pulled -up with a 50k
resistor.
57
D[6]
RXJA
I/O
I
Data Bus[6]
.
Microprocessor read/write data bus.
Receive Jitter Attenuator Select
.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the
receive path and connect Low to disable jitter attenuator.
Setting TXJA simultaneously "High" also disables jitter attenuator selection.
N
OTE
:
Internally pulled -up with a 50k
resistor.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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PDF描述
XRT82L38 Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）)
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