
á
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
II
Figure 15. ITU G.703 E1 Pulse Template .............................................................................................. 25
T
ABLE
8: DS1 I
NTERFACE
I
SOLATED
PULSE
MASK
AND
CORNER
POINTS
. .................................................... 26
Figure 16. DSX-1 Pulse Template ......................................................................................................... 26
T
ABLE
9: DC E
LECTRICAL
C
HARACTERISTICS
............................................................................................ 27
T
ABLE
10: P
OWER
C
ONSUMPTION
............................................................................................................. 27
ABSOLUTE MAXIMUM RATINGS ................................................................................... 27
T
ABLE
11: AC E
LECTRICAL
C
HARACTERISTICS
.......................................................................................... 28
Figure 17. Transmit Clock and Input Data Timing .............................................................................. 28
Figure 18. Receive Clock and Output Data Timing. ............................................................................ 29
T
ABLE
12: M
ICROPROCESSOR
INTERFACE
SIGNAL
...................................................................................... 30
T
ABLE
13: M
ICROPROCESSOR
R
EGISTER
M
AP
........................................................................................... 31
T
ABLE
14: C
OMMAND
C
ONTROL
R
EGISTER
0 ............................................................................................. 32
T
ABLE
15: C
OMMAND
C
ONTROL
R
EGISTER
1 ............................................................................................. 33
T
ABLE
16: C
HANNEL
S
TATUS
R
EGISTER
.................................................................................................... 34
T
ABLE
17: C
HANNEL
M
ASK
R
EGISTER
....................................................................................................... 35
T
ABLE
18: C
HANNEL
C
ONTROL
R
EGISTER
................................................................................................ 36
Figure 19. Intel Interface Timing (Read) ............................................................................................... 37
Figure 20. Intel Interface Timing (Write) ............................................................................................... 37
T
ABLE
19: I
NTEL
I
NTERFACE
T
IMING
S
PECIFICATIONS
................................................................................. 38
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ... 39
Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ... 39
Figure 23. Microprocessor Interface Timing - Reset Pulse Width ..................................................... 39
T
ABLE
20: M
OTOROLA
I
NTERFACE
T
IMING
S
PECIFICATION
.......................................................................... 40
J
ITTER
T
OLERANCE
IN
DS1
APPLICATIONS
.................................................................................................. 41
Figure 24. Input Jitter Tolerance performance of the XRT82L34, for DS1 Applications, with the Jitter
Attenuator Disabled .............................................................................................................. 41
J
ITTER
A
TTENUATOR
E
NABLED
AND
C
ONFIGURED
TO
O
PERATE
IN
THE
R
ECEIVE
P
ATH
................................. 42
Figure 25. Input Jitter Tolerance Capability of the XRT82L34 for DS1 Applications with the Jitter At-
tenuator Enabled and operating in the Receive Path ........................................................ 42
J
ITTER
T
RANSFER
C
HARACTERISTICS
OF
THE
XRT82L34
CONFIGURED
TO
OPERATE
IN
THE
DS1 M
ODE
...... 43
Figure 26. Jitter Transfer Characteristics of the XRT82L34 for DS1 Applications with the Jitter Atten-
uator Enabled and Operating in the Receive Path ............................................................. 43
APPENDIX A ..................................................................................................................... 44
XRT82LL34
AND
XRT82L24 E
VALUATION
K
IT
(XRT82L34/L24EVAL) ...................................................... 44
Figure 27. XRT82L34/L24 GUI Software Interface for Evaluating the XRT82L24/L34EVAL Application
Board ...................................................................................................................................... 44
Figure 28. Photograph of the XRT82L34/L24EVAL Application Board ............................................. 45
Figure 29. Block Layout of the XRT82L34/L24EVAL Application Board ........................................... 46
O
RDERING
I
NFORMATION
............................................................................................................................ 47
P
ACKAGE
D
IMENSIONS
100 L
EAD
TQFP 14
X
14
MM
..................................................................................... 47
R
EVISION
H
ISTORY
..................................................................................................................................... 48