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參數(shù)資料
| 型號(hào)： | XRT82L34 |
| 廠商： | Exar Corporation |
| 英文描述： | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
| 中文描述： | 四路T1/E1/J1收發(fā)線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器（四的T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）） |
| 文件頁數(shù)： | 12/50頁 |
| 文件大?。?/td> | 648K |
| 代理商： | XRT82L34 |
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XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
á
PRELIMINARY
10
66
MCLK
I
Master Clock Input
.
This signal is an independent 2.048MHz clock for E1 and 1.544Mhz clock for T1
system with accuracy better than ±50ppm and duty cycle within 40% to 60%.
The function of MCLK is to provide internal timing for the PLL clock recovery cir-
cuit, jitter attenuator block, reference clock during transmit all ones data and tim-
ing reference for the microprocessor in Host Mode operation.
If MCLK is not present for more than 10 μs the transmitter will be powered down
and the output will be tri-stated.
N
OTE
:
Internally pulled -up with a 50k
resistor.
67
A[3]
RXMUTE
I
I
Host Mode, Microprocessor Interface Address Bus[3].
Hardware Mode, Receive Muting
:
Connect this pin "High" to mute RxPOS/RxNEG output to a low state upon
receive LOS condition to prevent data chattering. Connect Low to disable mut-
ing function.
N
OTE
:
Internally pulled -up with a 50k
resistor.
68
A[2]
ECA
I
I
Host Mode, Microprocessor Interface Address Bus[2]
Hardware Mode, Transmit Equalizer Control A
This pin together with ECB and ECC are used for controlling transmit pulse
shaping and also selects T1 or E1 Mode of operation.
See Table 2
N
OTES
:
1. All transmit channels in T1 mode share the same pulse setting in Hard-
ware Mode.
2. Internally pulled -up with a 50k
resistor.
69
A[1]
ECB
I
I
Host Mode, Microprocessor Interface Address Bus [1].
Hardware Mode, Transmit Equalizer Control B
This pin together with ECA and ECC are used for controlling transmit pulse
shaping and also selects T1 or E1 Mode of operation.
N
OTE
:
Internally pulled -up with a 50k
resistor.
70
A[0]
ECC
I
I
Host Mode, Microprocessor Interface Address Bus [0].
Hardware Mode, Transmit Equalizer Control C
This pin together with ECB and ECA are used for controlling transmit pulse
shaping and also selects T1 or E1 Mode of operation.
N
OTE
:
Internally pulled -up with a 50k
resistor.
71
TxClk3
I
Transmitter 3 Clock Input
.
E1 rate at 2.048MHz ± 50ppm T1 rate at 1.544MHz ± 32ppm (see pin 5 descrip-
tion for other usage of this pin.)
72
TxPOS3/
TData3
I
Transmitter 3 Positive Data Input
.
In dual-rail mode, this signal is the p-rail input data for transmitter 3.
Transmitter 3 NRZ Data Input
.
In single-rail mode, this pin is used as the NRZ input data for transmitter 3.
N
OTE
:
Internally pulled -up with a 50k
resistor.
73
TxNEG3
I
Transmitter 3 Negative Data Input
.
In dual-rail mode, this signal is the negative NRZ data input for transmitter 3. In
single-rail mode, this pin can be left unconnected.
N
OTE
:
Internally pulled -up with a 50k
resistor.
74
RxLOS3
O
Receiver 3 Loss of Signal
.
This signal is asserted "High" to indicate loss of signal at the receive input.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
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| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
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| XRT83D10IW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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