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XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.5
19
modes. In Hardware Mode, HDB3, B8ZS or AMI cod-
ing selection is determined by the state of pin 10.
TRANSMIT PULSE SHAPER
The transmit pulse shaper uses high a speed clock
derived from MCLK to synthesize the shape and
width of the transmitted pulse applied to TTIP and
TRING. The internal high speed timing generator
eliminates the need for a tightly controlled transmit
clock TxClk duty cycle. In a T1 system, three control
bits (ECC, ECB and ECA) are available in the Host
Mode, for every channel to select 5 different cable
length pulse settings to meet DSX-1 pulse template.
Table 2 summaries the function of these control bits.
In Hardware Mode, all 4 transmit channels share the
same pulse synthesizer control settings.
DRIVER MONITOR
The driver monitor circuit is used for detecting trans-
mit driver failure by monitoring the activity at TTIP
and TRING. Driver failure may be caused by a short-
circuit in the primary of the transformer or system
problems at the input.
In the Host Mode, when the driver monitor detects no
transitions at TTIP and TRING for more than 128
clock cycles, the DMO bit in the interface register is
set and results in an interrupt (INT) to be generated.
Driver monitor function is not supported in Hardware
Mode.
TxPOS/TDATA and TxNEG Polarity
In HOST Mode, transmit data at TxPOS/TDATA and
TxNEG can be configured for active Low or active
High operation, by controlling the state of the DATAP
bit in the interface register. Writing a "0" to this bit se-
lects active High data and a "1" selects active Low
data. This control bit also selects receive output data
polarity (see Receive Data Invert Mode description).
This feature is not supported in Hardware Mode.
TRANSMIT OFF CONTROL
Each transmit channel of the line interface can be
shut down by writing a "1" to TxOFF in the channel
control interface register. In the “Transmitter off”
mode, the entire transmitter is disabled and the out-
puts at TTIP and TRING are placed in a high imped-
ance state. In Hardware Mode, pins 14 through pin 17
are used for powering down each transmit channel in-
dependently. If MCLK is missing, then all transmitters
will be powered down and the outputs are tri-stated.
INTERFACING THE XRT82L34 TO THE LINE
The XRT82L34 in E1 configuration can be transform-
er coupled to 75
coaxial or 120
twisted pair lines
as shown in Figure 12 and Figure 13 below. For DS3
applications connecting to a 100
twisted pair line is
shown in Figure 14.
T
ABLE
1: E
XAMPLES
OF
B8ZS E
NCODING
C
ASE
1
P
RECEDING
P
ULSE
N
EXT
8 B
ITS
Input
+
00000000
B8ZS
000VB0VB
AMI Output
+
000+ -0- +
Case 2
Input
-
00000000
B8ZS
000VB0VB
AMI Output
-
000- +0+ -
T
ABLE
2: T
RANSMIT
E
QUALIZER
C
ONTROL
ECC
ECB
ECA
S
YSTEM
C
ABLE
L
ENGTH
C
ODES
0
0
0
T1
0-133 ft.
B8ZS/AMI (DS1)
0
0
1
T1
133-266 ft.
B8ZS/AMI (DS1)
0
1
0
T1
266-399 ft.
B8ZS/AMI (DS1)
0
1
1
T1
399-533 ft.
B8ZS/AMI (DS1)
1
0
0
T1
533-655 ft.
B8ZS/AMI (DS1)
1
0
1
Not used
1
1
0
Not used
1
1
1
E1
--
HDB3/AMI (E1)