參數(shù)資料
型號(hào): XRT82L34
廠商: Exar Corporation
英文描述: Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器(帶時(shí)鐘恢復(fù)和振蕩衰減器))
中文描述: 四路T1/E1/J1收發(fā)線收發(fā)器時(shí)鐘恢復(fù)和抖動(dòng)衰減器(四的T1/E1/J1線收發(fā)器(帶時(shí)鐘恢復(fù)和振蕩衰減器))
文件頁數(shù): 34/50頁
文件大?。?/td> 648K
代理商: XRT82L34
XRT82L34
QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.5
á
PRELIMINARY
32
T
ABLE
14: C
OMMAND
C
ONTROL
R
EGISTER
0
C
OMMAND
C
ONTROL
R
EGISTER
0
P
ARALLEL
P
ORT
A
DDRESS
: 0000
B
IT
N
O
.
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
7
SR/DR
Single/Dual Rail:
Writing a "1" to this bit selects transmit and receive data format in
single-rail mode. In this mode, HDB3/B8ZS/AMI encoder and
decoder are available.
Writing a "0" selects dual-rail mode.
R/W
0
6
ATAOS
Automatic Transmit “All Ones”:
Writing a “1” in this bit position enables the automatic transmission
of an all one AMI pattern from the transmitter of any channel that
the receiver of that channel detects an LOS condition.
Writing a “0” in this bit position disables this feature.
R/W
0
5
RCLKE
RxClk Clock Edge: Writing a "1" to this bit selects receive output
data to be updated on positive edge of RxClk.
Writing a "0" to this bit selects the negative edge of RxClk.
R/W
0
4
TCLKE
TxClk Clock Edge: Writing a "1" to this bit selects positive edge of
TxClk to sample input data.
Write "0" to select negative edge.
R/W
0
3
DATAP
DATA Polarity: Writing a "0" to this bit selects transmit input and
receive output data to be active-high.
Write "1" to select active-low.
R/W
0
2
CODES
Coding/Decoding Select: This bit is used in conjunction with SR/DR
bit 1. If SR/DR is "1", writing a "0" to this bit selects HDB3 coding in
E1 and B8ZS in T1. Writing a "1" to this bit position selects AMI
code.
R/W
0
1
GIE
Global Interrupt Enable: Writing a "0" to this bit globally disables
interrupt generation caused by any alarm generated within the line
interface. Write a "1" to enable interrupt generation.
R/W
0
0
SRESET
Software Reset: Writing a "1" to this bit longer than 10μs initiates a
device reset through the microprocessor interface. All internal cir-
cuits are placed in the reset state with this bit set to a "1" except the
microprocessor register bits.
R/W
0
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XRT82L38 Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器(帶時(shí)鐘恢復(fù)和振蕩衰減器))
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