
XRT7245
DS3 UNI FOR ATM
á
PRELIMINARY
REV. 1.03
96
Bit 2—0—LSS(2:0)
This “Read/Write” bit-fields allows the user to trans-
mit their own “proprietary” data link messages, via
the 3 unused bits within the G1 bytes, of each out-
bound PLCP frame.
3.3.2.76
Rx CP Configuration Register
Bit 7—RxLCD (Loss of Cell Delineation)
This “Read Only” bit-field indicates whether or not the
Receive Cell Processor is experiencing a “Loss of Cell
Delineation”.
If this bit-field is “0”, then the Receive Cell Processor is
NOT experiencing a “Loss of Cell Delineation” and is
properly delineating the ATM cell data that it receives
from the Receive DS3 Framer.
If this bit-field is “1”, then the Receive Cell Processor is
experiencing a “Loss of Cell Delineation” and is NOT
properly delineating the ATM cell data that it receives
from the Receive DS3 Framer.
Note:
The content of this bit-field is irrelevant when the
UNI is operating in the PLCP Mode.
For more information on Cell Delineation by the
Receive Cell Processor, please see Section 7.3.2.1.2.
Bit 6—RDPChk (Receive “Data Path Integrity
Check”)Pattern
The “Read/Write” bit-field allows the user to select
which of two possible “Data Path Integrity Check” pat-
terns that the Receive Cell Processor will insert into the
fifth octet of each cell that is written into the RxFIFO.
The “Data Path Integrity Check” pattern options are:
An alternating pattern of 55h/AAh.
A constant pattern of 55h.
Writing a “0” to this bit-field selects the alternating
pattern. Writing a “1” to this bit-field selects the con-
stant pattern.
Note:
This bit-field is ignored if Bit 5 (of this register) is set
to “0”.
Bit 5—RDPChk (Receive “Data Path Integrity
Check”) Pattern Enable
This “Read/Write” bit-field allows the user to enable or
disable the insertion of the “Data Path Integrity Check”
pattern into the 5th octet of each cell that is written in-
to the RxFIFO.
Writing a “0” into this bit-field disables the insertion of
the “Data Path Integrity Check” pattern into the 5th
octet of the cell (e.g., the cell, with its HEC byte, will
be written into the RxFIFO).
Conversely, writing a “1” into this bit-field enables this
feature (e.g., the HEC byte of each cell will be over-
written by the “Data Path Integrity Check” pattern).
The “Data Path Integrity Check” pattern that is written
into the cell depends upon the setting of Bit 6 (RD-
PChk) within this register.
For more information on this topic, please see
Section 7.3.2.6.
Bit 4—IC (Idle Cell) Discard
This “Read/Write” bit-field allows the user to configure
the Receive Cell Processor to either discard or retain
Idle Cells. If the user configures the Receive Cell
Processor to discard Idle Cells, then the Idle Cells
will be discarded and NOT written to the Rx FIFO. If
the user configures the Receive Cell Processor to re-
tain Idle Cells, then all Idle Cells will be retained and
can be (depending upon the User Cell Filter settings)
written to the Rx FIFO.
Writing a “0” to this bit-field configures the Receive
Cell Processor to retain Idle Cells. Writing a “1” to
this bit-field configures the Receive Cell Processor to
discard Idle Cells.
For more information on the handling of Idle Cells by
the Receive Cell Processor, please see Section
7.3.2.3.1.
Bit 3—OAM Check Bit
This “Read/Write” bit-field allows the user to configure
the Receive Cell Processor to “check” the next OAM
cell that it receives. Specifically, this means that the
Address = 4Ch, Rx CP Configuration Register
B
IT
7
B
IT
6
B
IT
5
B
IT
4
B
IT
3
B
IT
2
B
IT
1
B
IT
0
RxLCD
RDPChk Pat
RDPChk Pat
Enable
IC Discard
OAM Check
Bit
De-Scramble
Enable
Rx Coset
Enable
HEC Error
Ignore
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
1
1
1
0